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RTXI 1.3
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RTXI 1.3
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00001 /* 00002 module/ni_stc.h 00003 Register descriptions for NI DAQ-STC chip 00004 00005 COMEDI - Linux Control and Measurement Device Interface 00006 Copyright (C) 1998-9 David A. Schleef <ds@schleef.org> 00007 00008 This program is free software; you can redistribute it and/or modify 00009 it under the terms of the GNU General Public License as published by 00010 the Free Software Foundation; either version 2 of the License, or 00011 (at your option) any later version. 00012 00013 This program is distributed in the hope that it will be useful, 00014 but WITHOUT ANY WARRANTY; without even the implied warranty of 00015 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00016 GNU General Public License for more details. 00017 00018 You should have received a copy of the GNU General Public License 00019 along with this program; if not, write to the Free Software 00020 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 00021 00022 */ 00023 00024 /* 00025 References: 00026 DAQ-STC Technical Reference Manual 00027 */ 00028 00029 #ifndef _COMEDI_NI_STC_H 00030 #define _COMEDI_NI_STC_H 00031 00032 #include "ni_tio.h" 00033 00034 #define _bit15 0x8000 00035 #define _bit14 0x4000 00036 #define _bit13 0x2000 00037 #define _bit12 0x1000 00038 #define _bit11 0x0800 00039 #define _bit10 0x0400 00040 #define _bit9 0x0200 00041 #define _bit8 0x0100 00042 #define _bit7 0x0080 00043 #define _bit6 0x0040 00044 #define _bit5 0x0020 00045 #define _bit4 0x0010 00046 #define _bit3 0x0008 00047 #define _bit2 0x0004 00048 #define _bit1 0x0002 00049 #define _bit0 0x0001 00050 00051 #define NUM_PFI_OUTPUT_SELECT_REGS 6 00052 00053 /* Registers in the National Instruments DAQ-STC chip */ 00054 00055 #define Interrupt_A_Ack_Register 2 00056 #define G0_Gate_Interrupt_Ack _bit15 00057 #define G0_TC_Interrupt_Ack _bit14 00058 #define AI_Error_Interrupt_Ack _bit13 00059 #define AI_STOP_Interrupt_Ack _bit12 00060 #define AI_START_Interrupt_Ack _bit11 00061 #define AI_START2_Interrupt_Ack _bit10 00062 #define AI_START1_Interrupt_Ack _bit9 00063 #define AI_SC_TC_Interrupt_Ack _bit8 00064 #define AI_SC_TC_Error_Confirm _bit7 00065 #define G0_TC_Error_Confirm _bit6 00066 #define G0_Gate_Error_Confirm _bit5 00067 00068 #define AI_Status_1_Register 2 00069 #define Interrupt_A_St 0x8000 00070 #define AI_FIFO_Full_St 0x4000 00071 #define AI_FIFO_Half_Full_St 0x2000 00072 #define AI_FIFO_Empty_St 0x1000 00073 #define AI_Overrun_St 0x0800 00074 #define AI_Overflow_St 0x0400 00075 #define AI_SC_TC_Error_St 0x0200 00076 #define AI_START2_St 0x0100 00077 #define AI_START1_St 0x0080 00078 #define AI_SC_TC_St 0x0040 00079 #define AI_START_St 0x0020 00080 #define AI_STOP_St 0x0010 00081 #define G0_TC_St 0x0008 00082 #define G0_Gate_Interrupt_St 0x0004 00083 #define AI_FIFO_Request_St 0x0002 00084 #define Pass_Thru_0_Interrupt_St 0x0001 00085 00086 #define AI_Status_2_Register 5 00087 00088 #define Interrupt_B_Ack_Register 3 00089 enum Interrupt_B_Ack_Bits { 00090 G1_Gate_Error_Confirm = _bit1, 00091 G1_TC_Error_Confirm = _bit2, 00092 AO_BC_TC_Trigger_Error_Confirm = _bit3, 00093 AO_BC_TC_Error_Confirm = _bit4, 00094 AO_UI2_TC_Error_Confrim = _bit5, 00095 AO_UI2_TC_Interrupt_Ack = _bit6, 00096 AO_UC_TC_Interrupt_Ack = _bit7, 00097 AO_BC_TC_Interrupt_Ack = _bit8, 00098 AO_START1_Interrupt_Ack = _bit9, 00099 AO_UPDATE_Interrupt_Ack = _bit10, 00100 AO_START_Interrupt_Ack = _bit11, 00101 AO_STOP_Interrupt_Ack = _bit12, 00102 AO_Error_Interrupt_Ack = _bit13, 00103 G1_TC_Interrupt_Ack = _bit14, 00104 G1_Gate_Interrupt_Ack = _bit15 00105 }; 00106 00107 #define AO_Status_1_Register 3 00108 #define Interrupt_B_St _bit15 00109 #define AO_FIFO_Full_St _bit14 00110 #define AO_FIFO_Half_Full_St _bit13 00111 #define AO_FIFO_Empty_St _bit12 00112 #define AO_BC_TC_Error_St _bit11 00113 #define AO_START_St _bit10 00114 #define AO_Overrun_St _bit9 00115 #define AO_START1_St _bit8 00116 #define AO_BC_TC_St _bit7 00117 #define AO_UC_TC_St _bit6 00118 #define AO_UPDATE_St _bit5 00119 #define AO_UI2_TC_St _bit4 00120 #define G1_TC_St _bit3 00121 #define G1_Gate_Interrupt_St _bit2 00122 #define AO_FIFO_Request_St _bit1 00123 #define Pass_Thru_1_Interrupt_St _bit0 00124 00125 #define AI_Command_2_Register 4 00126 #define AI_End_On_SC_TC _bit15 00127 #define AI_End_On_End_Of_Scan _bit14 00128 #define AI_START1_Disable _bit11 00129 #define AI_SC_Save_Trace _bit10 00130 #define AI_SI_Switch_Load_On_SC_TC _bit9 00131 #define AI_SI_Switch_Load_On_STOP _bit8 00132 #define AI_SI_Switch_Load_On_TC _bit7 00133 #define AI_SC_Switch_Load_On_TC _bit4 00134 #define AI_STOP_Pulse _bit3 00135 #define AI_START_Pulse _bit2 00136 #define AI_START2_Pulse _bit1 00137 #define AI_START1_Pulse _bit0 00138 00139 #define AO_Command_2_Register 5 00140 #define AO_End_On_BC_TC(x) (((x) & 0x3) << 14) 00141 #define AO_Start_Stop_Gate_Enable _bit13 00142 #define AO_UC_Save_Trace _bit12 00143 #define AO_BC_Gate_Enable _bit11 00144 #define AO_BC_Save_Trace _bit10 00145 #define AO_UI_Switch_Load_On_BC_TC _bit9 00146 #define AO_UI_Switch_Load_On_Stop _bit8 00147 #define AO_UI_Switch_Load_On_TC _bit7 00148 #define AO_UC_Switch_Load_On_BC_TC _bit6 00149 #define AO_UC_Switch_Load_On_TC _bit5 00150 #define AO_BC_Switch_Load_On_TC _bit4 00151 #define AO_Mute_B _bit3 00152 #define AO_Mute_A _bit2 00153 #define AO_UPDATE2_Pulse _bit1 00154 #define AO_START1_Pulse _bit0 00155 00156 #define AO_Status_2_Register 6 00157 00158 #define DIO_Parallel_Input_Register 7 00159 00160 #define AI_Command_1_Register 8 00161 #define AI_Analog_Trigger_Reset _bit14 00162 #define AI_Disarm _bit13 00163 #define AI_SI2_Arm _bit12 00164 #define AI_SI2_Load _bit11 00165 #define AI_SI_Arm _bit10 00166 #define AI_SI_Load _bit9 00167 #define AI_DIV_Arm _bit8 00168 #define AI_DIV_Load _bit7 00169 #define AI_SC_Arm _bit6 00170 #define AI_SC_Load _bit5 00171 #define AI_SCAN_IN_PROG_Pulse _bit4 00172 #define AI_EXTMUX_CLK_Pulse _bit3 00173 #define AI_LOCALMUX_CLK_Pulse _bit2 00174 #define AI_SC_TC_Pulse _bit1 00175 #define AI_CONVERT_Pulse _bit0 00176 00177 #define AO_Command_1_Register 9 00178 #define AO_Analog_Trigger_Reset _bit15 00179 #define AO_START_Pulse _bit14 00180 #define AO_Disarm _bit13 00181 #define AO_UI2_Arm_Disarm _bit12 00182 #define AO_UI2_Load _bit11 00183 #define AO_UI_Arm _bit10 00184 #define AO_UI_Load _bit9 00185 #define AO_UC_Arm _bit8 00186 #define AO_UC_Load _bit7 00187 #define AO_BC_Arm _bit6 00188 #define AO_BC_Load _bit5 00189 #define AO_DAC1_Update_Mode _bit4 00190 #define AO_LDAC1_Source_Select _bit3 00191 #define AO_DAC0_Update_Mode _bit2 00192 #define AO_LDAC0_Source_Select _bit1 00193 #define AO_UPDATE_Pulse _bit0 00194 00195 #define DIO_Output_Register 10 00196 #define DIO_Parallel_Data_Out(a) ((a)&0xff) 00197 #define DIO_Parallel_Data_Mask 0xff 00198 #define DIO_SDOUT _bit0 00199 #define DIO_SDIN _bit4 00200 #define DIO_Serial_Data_Out(a) (((a)&0xff)<<8) 00201 #define DIO_Serial_Data_Mask 0xff00 00202 00203 #define DIO_Control_Register 11 00204 #define DIO_Software_Serial_Control _bit11 00205 #define DIO_HW_Serial_Timebase _bit10 00206 #define DIO_HW_Serial_Enable _bit9 00207 #define DIO_HW_Serial_Start _bit8 00208 #define DIO_Pins_Dir(a) ((a)&0xff) 00209 #define DIO_Pins_Dir_Mask 0xff 00210 00211 #define AI_Mode_1_Register 12 00212 #define AI_CONVERT_Source_Select(a) (((a) & 0x1f) << 11) 00213 #define AI_SI_Source_select(a) (((a) & 0x1f) << 6) 00214 #define AI_CONVERT_Source_Polarity _bit5 00215 #define AI_SI_Source_Polarity _bit4 00216 #define AI_Start_Stop _bit3 00217 #define AI_Mode_1_Reserved _bit2 00218 #define AI_Continuous _bit1 00219 #define AI_Trigger_Once _bit0 00220 00221 #define AI_Mode_2_Register 13 00222 #define AI_SC_Gate_Enable _bit15 00223 #define AI_Start_Stop_Gate_Enable _bit14 00224 #define AI_Pre_Trigger _bit13 00225 #define AI_External_MUX_Present _bit12 00226 #define AI_SI2_Initial_Load_Source _bit9 00227 #define AI_SI2_Reload_Mode _bit8 00228 #define AI_SI_Initial_Load_Source _bit7 00229 #define AI_SI_Reload_Mode(a) (((a) & 0x7)<<4) 00230 #define AI_SI_Write_Switch _bit3 00231 #define AI_SC_Initial_Load_Source _bit2 00232 #define AI_SC_Reload_Mode _bit1 00233 #define AI_SC_Write_Switch _bit0 00234 00235 #define AI_SI_Load_A_Registers 14 00236 #define AI_SI_Load_B_Registers 16 00237 #define AI_SC_Load_A_Registers 18 00238 #define AI_SC_Load_B_Registers 20 00239 #define AI_SI_Save_Registers 64 00240 #define AI_SC_Save_Registers 66 00241 00242 #define AI_SI2_Load_A_Register 23 00243 #define AI_SI2_Load_B_Register 25 00244 00245 #define Joint_Status_1_Register 27 00246 #define DIO_Serial_IO_In_Progress_St _bit12 00247 00248 #define DIO_Serial_Input_Register 28 00249 #define Joint_Status_2_Register 29 00250 enum Joint_Status_2_Bits { 00251 AO_TMRDACWRs_In_Progress_St = 0x20, 00252 }; 00253 00254 #define AO_Mode_1_Register 38 00255 #define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11) 00256 #define AO_UI_Source_Select(x) (((x)&0x1f)<<6) 00257 #define AO_Multiple_Channels _bit5 00258 #define AO_UPDATE_Source_Polarity _bit4 00259 #define AO_UI_Source_Polarity _bit3 00260 #define AO_UC_Switch_Load_Every_TC _bit2 00261 #define AO_Continuous _bit1 00262 #define AO_Trigger_Once _bit0 00263 00264 #define AO_Mode_2_Register 39 00265 #define AO_FIFO_Mode_Mask ( 0x3 << 14 ) 00266 enum AO_FIFO_Mode_Bits { 00267 AO_FIFO_Mode_HF_to_F = (3 << 14), 00268 AO_FIFO_Mode_F = (2 << 14), 00269 AO_FIFO_Mode_HF = (1 << 14), 00270 AO_FIFO_Mode_E = (0 << 14), 00271 }; 00272 #define AO_FIFO_Retransmit_Enable _bit13 00273 #define AO_START1_Disable _bit12 00274 #define AO_UC_Initial_Load_Source _bit11 00275 #define AO_UC_Write_Switch _bit10 00276 #define AO_UI2_Initial_Load_Source _bit9 00277 #define AO_UI2_Reload_Mode _bit8 00278 #define AO_UI_Initial_Load_Source _bit7 00279 #define AO_UI_Reload_Mode(x) (((x) & 0x7) << 4) 00280 #define AO_UI_Write_Switch _bit3 00281 #define AO_BC_Initial_Load_Source _bit2 00282 #define AO_BC_Reload_Mode _bit1 00283 #define AO_BC_Write_Switch _bit0 00284 00285 #define AO_UI_Load_A_Register 40 00286 #define AO_UI_Load_A_Register_High 40 00287 #define AO_UI_Load_A_Register_Low 41 00288 #define AO_UI_Load_B_Register 42 00289 #define AO_UI_Save_Registers 16 00290 #define AO_BC_Load_A_Register 44 00291 #define AO_BC_Load_A_Register_High 44 00292 #define AO_BC_Load_A_Register_Low 45 00293 #define AO_BC_Load_B_Register 46 00294 #define AO_BC_Load_B_Register_High 46 00295 #define AO_BC_Load_B_Register_Low 47 00296 #define AO_BC_Save_Registers 18 00297 #define AO_UC_Load_A_Register 48 00298 #define AO_UC_Load_A_Register_High 48 00299 #define AO_UC_Load_A_Register_Low 49 00300 #define AO_UC_Load_B_Register 50 00301 #define AO_UC_Save_Registers 20 00302 00303 #define Clock_and_FOUT_Register 56 00304 enum Clock_and_FOUT_bits { 00305 FOUT_Enable = _bit15, 00306 FOUT_Timebase_Select = _bit14, 00307 DIO_Serial_Out_Divide_By_2 = _bit13, 00308 Slow_Internal_Time_Divide_By_2 = _bit12, 00309 Slow_Internal_Timebase = _bit11, 00310 G_Source_Divide_By_2 = _bit10, 00311 Clock_To_Board_Divide_By_2 = _bit9, 00312 Clock_To_Board = _bit8, 00313 AI_Output_Divide_By_2 = _bit7, 00314 AI_Source_Divide_By_2 = _bit6, 00315 AO_Output_Divide_By_2 = _bit5, 00316 AO_Source_Divide_By_2 = _bit4, 00317 FOUT_Divider_mask = 0xf 00318 }; 00319 static inline unsigned FOUT_Divider(unsigned divider) 00320 { 00321 return (divider & FOUT_Divider_mask); 00322 } 00323 00324 #define IO_Bidirection_Pin_Register 57 00325 #define RTSI_Trig_Direction_Register 58 00326 enum RTSI_Trig_Direction_Bits { 00327 Drive_RTSI_Clock_Bit = 0x1, 00328 Use_RTSI_Clock_Bit = 0x2, 00329 }; 00330 static inline unsigned RTSI_Output_Bit(unsigned channel, int is_mseries) 00331 { 00332 unsigned max_channel; 00333 unsigned base_bit_shift; 00334 if (is_mseries) { 00335 base_bit_shift = 8; 00336 max_channel = 7; 00337 } else { 00338 base_bit_shift = 9; 00339 max_channel = 6; 00340 } 00341 if (channel > max_channel) { 00342 rt_printk("%s: bug, invalid RTSI_channel=%i\n", __FUNCTION__, 00343 channel); 00344 return 0; 00345 } 00346 return 1 << (base_bit_shift + channel); 00347 } 00348 00349 #define Interrupt_Control_Register 59 00350 #define Interrupt_B_Enable _bit15 00351 #define Interrupt_B_Output_Select(x) ((x)<<12) 00352 #define Interrupt_A_Enable _bit11 00353 #define Interrupt_A_Output_Select(x) ((x)<<8) 00354 #define Pass_Thru_0_Interrupt_Polarity _bit3 00355 #define Pass_Thru_1_Interrupt_Polarity _bit2 00356 #define Interrupt_Output_On_3_Pins _bit1 00357 #define Interrupt_Output_Polarity _bit0 00358 00359 #define AI_Output_Control_Register 60 00360 #define AI_START_Output_Select _bit10 00361 #define AI_SCAN_IN_PROG_Output_Select(x) (((x) & 0x3) << 8) 00362 #define AI_EXTMUX_CLK_Output_Select(x) (((x) & 0x3) << 6) 00363 #define AI_LOCALMUX_CLK_Output_Select(x) ((x)<<4) 00364 #define AI_SC_TC_Output_Select(x) ((x)<<2) 00365 enum ai_convert_output_selection { 00366 AI_CONVERT_Output_High_Z = 0, 00367 AI_CONVERT_Output_Ground = 1, 00368 AI_CONVERT_Output_Enable_Low = 2, 00369 AI_CONVERT_Output_Enable_High = 3 00370 }; 00371 static unsigned AI_CONVERT_Output_Select(enum ai_convert_output_selection 00372 selection) 00373 { 00374 return selection & 0x3; 00375 } 00376 00377 #define AI_START_STOP_Select_Register 62 00378 #define AI_START_Polarity _bit15 00379 #define AI_STOP_Polarity _bit14 00380 #define AI_STOP_Sync _bit13 00381 #define AI_STOP_Edge _bit12 00382 #define AI_STOP_Select(a) (((a) & 0x1f)<<7) 00383 #define AI_START_Sync _bit6 00384 #define AI_START_Edge _bit5 00385 #define AI_START_Select(a) ((a) & 0x1f) 00386 00387 #define AI_Trigger_Select_Register 63 00388 #define AI_START1_Polarity _bit15 00389 #define AI_START2_Polarity _bit14 00390 #define AI_START2_Sync _bit13 00391 #define AI_START2_Edge _bit12 00392 #define AI_START2_Select(a) (((a) & 0x1f) << 7) 00393 #define AI_START1_Sync _bit6 00394 #define AI_START1_Edge _bit5 00395 #define AI_START1_Select(a) ((a) & 0x1f) 00396 00397 #define AI_DIV_Load_A_Register 64 00398 00399 #define AO_Start_Select_Register 66 00400 #define AO_UI2_Software_Gate _bit15 00401 #define AO_UI2_External_Gate_Polarity _bit14 00402 #define AO_START_Polarity _bit13 00403 #define AO_AOFREQ_Enable _bit12 00404 #define AO_UI2_External_Gate_Select(a) (((a) & 0x1f) << 7) 00405 #define AO_START_Sync _bit6 00406 #define AO_START_Edge _bit5 00407 #define AO_START_Select(a) ((a) & 0x1f) 00408 00409 #define AO_Trigger_Select_Register 67 00410 #define AO_UI2_External_Gate_Enable _bit15 00411 #define AO_Delayed_START1 _bit14 00412 #define AO_START1_Polarity _bit13 00413 #define AO_UI2_Source_Polarity _bit12 00414 #define AO_UI2_Source_Select(x) (((x)&0x1f)<<7) 00415 #define AO_START1_Sync _bit6 00416 #define AO_START1_Edge _bit5 00417 #define AO_START1_Select(x) (((x)&0x1f)<<0) 00418 00419 #define AO_Mode_3_Register 70 00420 #define AO_UI2_Switch_Load_Next_TC _bit13 00421 #define AO_UC_Switch_Load_Every_BC_TC _bit12 00422 #define AO_Trigger_Length _bit11 00423 #define AO_Stop_On_Overrun_Error _bit5 00424 #define AO_Stop_On_BC_TC_Trigger_Error _bit4 00425 #define AO_Stop_On_BC_TC_Error _bit3 00426 #define AO_Not_An_UPDATE _bit2 00427 #define AO_Software_Gate _bit1 00428 #define AO_Last_Gate_Disable _bit0 /* M Series only */ 00429 00430 #define Joint_Reset_Register 72 00431 #define Software_Reset _bit11 00432 #define AO_Configuration_End _bit9 00433 #define AI_Configuration_End _bit8 00434 #define AO_Configuration_Start _bit5 00435 #define AI_Configuration_Start _bit4 00436 #define G1_Reset _bit3 00437 #define G0_Reset _bit2 00438 #define AO_Reset _bit1 00439 #define AI_Reset _bit0 00440 00441 #define Interrupt_A_Enable_Register 73 00442 #define Pass_Thru_0_Interrupt_Enable _bit9 00443 #define G0_Gate_Interrupt_Enable _bit8 00444 #define AI_FIFO_Interrupt_Enable _bit7 00445 #define G0_TC_Interrupt_Enable _bit6 00446 #define AI_Error_Interrupt_Enable _bit5 00447 #define AI_STOP_Interrupt_Enable _bit4 00448 #define AI_START_Interrupt_Enable _bit3 00449 #define AI_START2_Interrupt_Enable _bit2 00450 #define AI_START1_Interrupt_Enable _bit1 00451 #define AI_SC_TC_Interrupt_Enable _bit0 00452 00453 #define Interrupt_B_Enable_Register 75 00454 #define Pass_Thru_1_Interrupt_Enable _bit11 00455 #define G1_Gate_Interrupt_Enable _bit10 00456 #define G1_TC_Interrupt_Enable _bit9 00457 #define AO_FIFO_Interrupt_Enable _bit8 00458 #define AO_UI2_TC_Interrupt_Enable _bit7 00459 #define AO_UC_TC_Interrupt_Enable _bit6 00460 #define AO_Error_Interrupt_Enable _bit5 00461 #define AO_STOP_Interrupt_Enable _bit4 00462 #define AO_START_Interrupt_Enable _bit3 00463 #define AO_UPDATE_Interrupt_Enable _bit2 00464 #define AO_START1_Interrupt_Enable _bit1 00465 #define AO_BC_TC_Interrupt_Enable _bit0 00466 00467 #define Second_IRQ_A_Enable_Register 74 00468 enum Second_IRQ_A_Enable_Bits { 00469 AI_SC_TC_Second_Irq_Enable = _bit0, 00470 AI_START1_Second_Irq_Enable = _bit1, 00471 AI_START2_Second_Irq_Enable = _bit2, 00472 AI_START_Second_Irq_Enable = _bit3, 00473 AI_STOP_Second_Irq_Enable = _bit4, 00474 AI_Error_Second_Irq_Enable = _bit5, 00475 G0_TC_Second_Irq_Enable = _bit6, 00476 AI_FIFO_Second_Irq_Enable = _bit7, 00477 G0_Gate_Second_Irq_Enable = _bit8, 00478 Pass_Thru_0_Second_Irq_Enable = _bit9 00479 }; 00480 00481 #define Second_IRQ_B_Enable_Register 76 00482 enum Second_IRQ_B_Enable_Bits { 00483 AO_BC_TC_Second_Irq_Enable = _bit0, 00484 AO_START1_Second_Irq_Enable = _bit1, 00485 AO_UPDATE_Second_Irq_Enable = _bit2, 00486 AO_START_Second_Irq_Enable = _bit3, 00487 AO_STOP_Second_Irq_Enable = _bit4, 00488 AO_Error_Second_Irq_Enable = _bit5, 00489 AO_UC_TC_Second_Irq_Enable = _bit6, 00490 AO_UI2_TC_Second_Irq_Enable = _bit7, 00491 AO_FIFO_Second_Irq_Enable = _bit8, 00492 G1_TC_Second_Irq_Enable = _bit9, 00493 G1_Gate_Second_Irq_Enable = _bit10, 00494 Pass_Thru_1_Second_Irq_Enable = _bit11 00495 }; 00496 00497 #define AI_Personal_Register 77 00498 #define AI_SHIFTIN_Pulse_Width _bit15 00499 #define AI_EOC_Polarity _bit14 00500 #define AI_SOC_Polarity _bit13 00501 #define AI_SHIFTIN_Polarity _bit12 00502 #define AI_CONVERT_Pulse_Timebase _bit11 00503 #define AI_CONVERT_Pulse_Width _bit10 00504 #define AI_CONVERT_Original_Pulse _bit9 00505 #define AI_FIFO_Flags_Polarity _bit8 00506 #define AI_Overrun_Mode _bit7 00507 #define AI_EXTMUX_CLK_Pulse_Width _bit6 00508 #define AI_LOCALMUX_CLK_Pulse_Width _bit5 00509 #define AI_AIFREQ_Polarity _bit4 00510 00511 #define AO_Personal_Register 78 00512 enum AO_Personal_Bits { 00513 AO_Interval_Buffer_Mode = 1 << 3, 00514 AO_BC_Source_Select = 1 << 4, 00515 AO_UPDATE_Pulse_Width = 1 << 5, 00516 AO_UPDATE_Pulse_Timebase = 1 << 6, 00517 AO_UPDATE_Original_Pulse = 1 << 7, 00518 AO_DMA_PIO_Control = 1 << 8, /* M Series: reserved */ 00519 AO_AOFREQ_Polarity = 1 << 9, /* M Series: reserved */ 00520 AO_FIFO_Enable = 1 << 10, 00521 AO_FIFO_Flags_Polarity = 1 << 11, /* M Series: reserved */ 00522 AO_TMRDACWR_Pulse_Width = 1 << 12, 00523 AO_Fast_CPU = 1 << 13, /* M Series: reserved */ 00524 AO_Number_Of_DAC_Packages = 1 << 14, // 1 for "single" mode, 0 for "dual" 00525 AO_Multiple_DACS_Per_Package = 1 << 15 // m-series only 00526 }; 00527 #define RTSI_Trig_A_Output_Register 79 00528 #define RTSI_Trig_B_Output_Register 80 00529 enum RTSI_Trig_B_Output_Bits { 00530 RTSI_Sub_Selection_1_Bit = 0x8000 // not for m-series 00531 }; 00532 static inline unsigned RTSI_Trig_Output_Bits(unsigned rtsi_channel, 00533 unsigned source) 00534 { 00535 return (source & 0xf) << ((rtsi_channel % 4) * 4); 00536 }; 00537 static inline unsigned RTSI_Trig_Output_Mask(unsigned rtsi_channel) 00538 { 00539 return 0xf << ((rtsi_channel % 4) * 4); 00540 }; 00541 00542 // inverse to RTSI_Trig_Output_Bits() 00543 static inline unsigned RTSI_Trig_Output_Source(unsigned rtsi_channel, 00544 unsigned bits) 00545 { 00546 return (bits >> ((rtsi_channel % 4) * 4)) & 0xf; 00547 }; 00548 00549 #define RTSI_Board_Register 81 00550 #define Write_Strobe_0_Register 82 00551 #define Write_Strobe_1_Register 83 00552 #define Write_Strobe_2_Register 84 00553 #define Write_Strobe_3_Register 85 00554 00555 #define AO_Output_Control_Register 86 00556 #define AO_External_Gate_Enable _bit15 00557 #define AO_External_Gate_Select(x) (((x)&0x1f)<<10) 00558 #define AO_Number_Of_Channels(x) (((x)&0xf)<<6) 00559 #define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4) 00560 #define AO_External_Gate_Polarity _bit3 00561 #define AO_UPDATE2_Output_Toggle _bit2 00562 enum ao_update_output_selection { 00563 AO_Update_Output_High_Z = 0, 00564 AO_Update_Output_Ground = 1, 00565 AO_Update_Output_Enable_Low = 2, 00566 AO_Update_Output_Enable_High = 3 00567 }; 00568 static unsigned AO_UPDATE_Output_Select(enum ao_update_output_selection 00569 selection) 00570 { 00571 return selection & 0x3; 00572 } 00573 00574 #define AI_Mode_3_Register 87 00575 #define AI_Trigger_Length _bit15 00576 #define AI_Delay_START _bit14 00577 #define AI_Software_Gate _bit13 00578 #define AI_SI_Special_Trigger_Delay _bit12 00579 #define AI_SI2_Source_Select _bit11 00580 #define AI_Delayed_START2 _bit10 00581 #define AI_Delayed_START1 _bit9 00582 #define AI_External_Gate_Mode _bit8 00583 #define AI_FIFO_Mode_HF_to_E (3<<6) 00584 #define AI_FIFO_Mode_F (2<<6) 00585 #define AI_FIFO_Mode_HF (1<<6) 00586 #define AI_FIFO_Mode_NE (0<<6) 00587 #define AI_External_Gate_Polarity _bit5 00588 #define AI_External_Gate_Select(a) ((a) & 0x1f) 00589 00590 #define G_Autoincrement_Register(a) (68+(a)) 00591 #define G_Command_Register(a) (6+(a)) 00592 #define G_HW_Save_Register(a) (8+(a)*2) 00593 #define G_HW_Save_Register_High(a) (8+(a)*2) 00594 #define G_HW_Save_Register_Low(a) (9+(a)*2) 00595 #define G_Input_Select_Register(a) (36+(a)) 00596 #define G_Load_A_Register(a) (28+(a)*4) 00597 #define G_Load_A_Register_High(a) (28+(a)*4) 00598 #define G_Load_A_Register_Low(a) (29+(a)*4) 00599 #define G_Load_B_Register(a) (30+(a)*4) 00600 #define G_Load_B_Register_High(a) (30+(a)*4) 00601 #define G_Load_B_Register_Low(a) (31+(a)*4) 00602 #define G_Mode_Register(a) (26+(a)) 00603 #define G_Save_Register(a) (12+(a)*2) 00604 #define G_Save_Register_High(a) (12+(a)*2) 00605 #define G_Save_Register_Low(a) (13+(a)*2) 00606 #define G_Status_Register 4 00607 #define Analog_Trigger_Etc_Register 61 00608 00609 /* command register */ 00610 #define G_Disarm_Copy _bit15 /* strobe */ 00611 #define G_Save_Trace_Copy _bit14 00612 #define G_Arm_Copy _bit13 /* strobe */ 00613 #define G_Bank_Switch_Start _bit10 /* strobe */ 00614 #define G_Little_Big_Endian _bit9 00615 #define G_Synchronized_Gate _bit8 00616 #define G_Write_Switch _bit7 00617 #define G_Up_Down(a) (((a)&0x03)<<5) 00618 #define G_Disarm _bit4 /* strobe */ 00619 #define G_Analog_Trigger_Reset _bit3 /* strobe */ 00620 #define G_Save_Trace _bit1 00621 #define G_Arm _bit0 /* strobe */ 00622 00623 /*channel agnostic names for the command register #defines */ 00624 #define G_Bank_Switch_Enable _bit12 00625 #define G_Bank_Switch_Mode _bit11 00626 #define G_Load _bit2 /* strobe */ 00627 00628 /* input select register */ 00629 #define G_Gate_Select(a) (((a)&0x1f)<<7) 00630 #define G_Source_Select(a) (((a)&0x1f)<<2) 00631 #define G_Write_Acknowledges_Irq _bit1 00632 #define G_Read_Acknowledges_Irq _bit0 00633 00634 /* same input select register, but with channel agnostic names */ 00635 #define G_Source_Polarity _bit15 00636 #define G_Output_Polarity _bit14 00637 #define G_OR_Gate _bit13 00638 #define G_Gate_Select_Load_Source _bit12 00639 00640 /* mode register */ 00641 #define G_Loading_On_TC _bit12 00642 #define G_Output_Mode(a) (((a)&0x03)<<8) 00643 #define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3) 00644 #define G_Gating_Mode(a) (((a)&0x03)<<0) 00645 00646 /* same input mode register, but with channel agnostic names */ 00647 #define G_Load_Source_Select _bit7 00648 #define G_Reload_Source_Switching _bit15 00649 #define G_Loading_On_Gate _bit14 00650 #define G_Gate_Polarity _bit13 00651 00652 #define G_Counting_Once(a) (((a)&0x03)<<10) 00653 #define G_Stop_Mode(a) (((a)&0x03)<<5) 00654 #define G_Gate_On_Both_Edges _bit2 00655 00656 /* G_Status_Register */ 00657 #define G1_Gate_Error_St _bit15 00658 #define G0_Gate_Error_St _bit14 00659 #define G1_TC_Error_St _bit13 00660 #define G0_TC_Error_St _bit12 00661 #define G1_No_Load_Between_Gates_St _bit11 00662 #define G0_No_Load_Between_Gates_St _bit10 00663 #define G1_Armed_St _bit9 00664 #define G0_Armed_St _bit8 00665 #define G1_Stale_Data_St _bit7 00666 #define G0_Stale_Data_St _bit6 00667 #define G1_Next_Load_Source_St _bit5 00668 #define G0_Next_Load_Source_St _bit4 00669 #define G1_Counting_St _bit3 00670 #define G0_Counting_St _bit2 00671 #define G1_Save_St _bit1 00672 #define G0_Save_St _bit0 00673 00674 /* general purpose counter timer */ 00675 #define G_Autoincrement(a) ((a)<<0) 00676 00677 /*Analog_Trigger_Etc_Register*/ 00678 #define Analog_Trigger_Mode(x) ((x) & 0x7) 00679 #define Analog_Trigger_Enable _bit3 00680 #define Analog_Trigger_Drive _bit4 00681 #define GPFO_1_Output_Select _bit7 00682 #define GPFO_0_Output_Select(a) ((a)<<11) 00683 #define GPFO_0_Output_Enable _bit14 00684 #define GPFO_1_Output_Enable _bit15 00685 00686 /* Additional windowed registers unique to E series */ 00687 00688 /* 16 bit registers shadowed from DAQ-STC */ 00689 #define Window_Address 0x00 00690 #define Window_Data 0x02 00691 00692 #define Configuration_Memory_Clear 82 00693 #define ADC_FIFO_Clear 83 00694 #define DAC_FIFO_Clear 84 00695 00696 /* i/o port offsets */ 00697 00698 /* 8 bit registers */ 00699 #define XXX_Status 0x01 00700 enum XXX_Status_Bits { 00701 PROMOUT = 0x1, 00702 AI_FIFO_LOWER_NOT_EMPTY = 0x8, 00703 }; 00704 #define Serial_Command 0x0d 00705 #define Misc_Command 0x0f 00706 #define Port_A 0x19 00707 #define Port_B 0x1b 00708 #define Port_C 0x1d 00709 #define Configuration 0x1f 00710 #define Strobes 0x01 00711 #define Channel_A_Mode 0x03 00712 #define Channel_B_Mode 0x05 00713 #define Channel_C_Mode 0x07 00714 #define AI_AO_Select 0x09 00715 enum AI_AO_Select_Bits { 00716 AI_DMA_Select_Shift = 0, 00717 AI_DMA_Select_Mask = 0xf, 00718 AO_DMA_Select_Shift = 4, 00719 AO_DMA_Select_Mask = 0xf << AO_DMA_Select_Shift 00720 }; 00721 #define G0_G1_Select 0x0b 00722 static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel) 00723 { 00724 if (channel < 4) 00725 return 1 << channel; 00726 if (channel == 4) 00727 return 0x3; 00728 if (channel == 5) 00729 return 0x5; 00730 BUG(); 00731 return 0; 00732 } 00733 static inline unsigned GPCT_DMA_Select_Bits(unsigned gpct_index, 00734 unsigned mite_channel) 00735 { 00736 BUG_ON(gpct_index > 1); 00737 return ni_stc_dma_channel_select_bitfield(mite_channel) << (4 * 00738 gpct_index); 00739 } 00740 static inline unsigned GPCT_DMA_Select_Mask(unsigned gpct_index) 00741 { 00742 BUG_ON(gpct_index > 1); 00743 return 0xf << (4 * gpct_index); 00744 } 00745 00746 /* 16 bit registers */ 00747 00748 #define Configuration_Memory_Low 0x10 00749 enum Configuration_Memory_Low_Bits { 00750 AI_DITHER = 0x200, 00751 AI_LAST_CHANNEL = 0x8000, 00752 }; 00753 #define Configuration_Memory_High 0x12 00754 enum Configuration_Memory_High_Bits { 00755 AI_AC_COUPLE = 0x800, 00756 AI_DIFFERENTIAL = 0x1000, 00757 AI_COMMON = 0x2000, 00758 AI_GROUND = 0x3000, 00759 }; 00760 static inline unsigned int AI_CONFIG_CHANNEL(unsigned int channel) 00761 { 00762 return (channel & 0x3f); 00763 } 00764 00765 #define ADC_FIFO_Data_Register 0x1c 00766 00767 #define AO_Configuration 0x16 00768 #define AO_Bipolar _bit0 00769 #define AO_Deglitch _bit1 00770 #define AO_Ext_Ref _bit2 00771 #define AO_Ground_Ref _bit3 00772 #define AO_Channel(x) ((x) << 8) 00773 00774 #define DAC_FIFO_Data 0x1e 00775 #define DAC0_Direct_Data 0x18 00776 #define DAC1_Direct_Data 0x1a 00777 00778 /* 611x registers (these boards differ from the e-series) */ 00779 00780 #define Magic_611x 0x19 /* w8 (new) */ 00781 #define Calibration_Channel_Select_611x 0x1a /* w16 (new) */ 00782 #define ADC_FIFO_Data_611x 0x1c /* r32 (incompatible) */ 00783 #define AI_FIFO_Offset_Load_611x 0x05 /* r8 (new) */ 00784 #define DAC_FIFO_Data_611x 0x14 /* w32 (incompatible) */ 00785 #define Cal_Gain_Select_611x 0x05 /* w8 (new) */ 00786 00787 #define AO_Window_Address_611x 0x18 00788 #define AO_Window_Data_611x 0x1e 00789 00790 /* 6143 registers */ 00791 #define Magic_6143 0x19 /* w8 */ 00792 #define G0G1_DMA_Select_6143 0x0B /* w8 */ 00793 #define PipelineDelay_6143 0x1f /* w8 */ 00794 #define EOC_Set_6143 0x1D /* w8 */ 00795 #define AIDMA_Select_6143 0x09 /* w8 */ 00796 #define AIFIFO_Data_6143 0x8C /* w32 */ 00797 #define AIFIFO_Flag_6143 0x84 /* w32 */ 00798 #define AIFIFO_Control_6143 0x88 /* w32 */ 00799 #define AIFIFO_Status_6143 0x88 /* w32 */ 00800 #define AIFIFO_DMAThreshold_6143 0x90 /* w32 */ 00801 #define AIFIFO_Words_Available_6143 0x94 /* w32 */ 00802 00803 #define Calibration_Channel_6143 0x42 /* w16 */ 00804 #define Calibration_LowTime_6143 0x20 /* w16 */ 00805 #define Calibration_HighTime_6143 0x22 /* w16 */ 00806 #define Relay_Counter_Load_Val__6143 0x4C /* w32 */ 00807 #define Signature_6143 0x50 /* w32 */ 00808 #define Release_Date_6143 0x54 /* w32 */ 00809 #define Release_Oldest_Date_6143 0x58 /* w32 */ 00810 00811 #define Calibration_Channel_6143_RelayOn 0x8000 /* Calibration relay switch On */ 00812 #define Calibration_Channel_6143_RelayOff 0x4000 /* Calibration relay switch Off */ 00813 #define Calibration_Channel_Gnd_Gnd 0x00 /* Offset Calibration */ 00814 #define Calibration_Channel_2v5_Gnd 0x02 /* 2.5V Reference */ 00815 #define Calibration_Channel_Pwm_Gnd 0x05 /* +/- 5V Self Cal */ 00816 #define Calibration_Channel_2v5_Pwm 0x0a /* PWM Calibration */ 00817 #define Calibration_Channel_Pwm_Pwm 0x0d /* CMRR */ 00818 #define Calibration_Channel_Gnd_Pwm 0x0e /* PWM Calibration */ 00819 00820 /* 671x, 611x registers */ 00821 00822 /* 671xi, 611x windowed ao registers */ 00823 enum windowed_regs_67xx_61xx { 00824 AO_Immediate_671x = 0x11, /* W 16 */ 00825 AO_Timed_611x = 0x10, /* W 16 */ 00826 AO_FIFO_Offset_Load_611x = 0x13, /* W32 */ 00827 AO_Later_Single_Point_Updates = 0x14, /* W 16 */ 00828 AO_Waveform_Generation_611x = 0x15, /* W 16 */ 00829 AO_Misc_611x = 0x16, /* W 16 */ 00830 AO_Calibration_Channel_Select_67xx = 0x17, /* W 16 */ 00831 AO_Configuration_2_67xx = 0x18, /* W 16 */ 00832 CAL_ADC_Command_67xx = 0x19, /* W 8 */ 00833 CAL_ADC_Status_67xx = 0x1a, /* R 8 */ 00834 CAL_ADC_Data_67xx = 0x1b, /* R 16 */ 00835 CAL_ADC_Config_Data_High_Word_67xx = 0x1c, /* RW 16 */ 00836 CAL_ADC_Config_Data_Low_Word_67xx = 0x1d, /* RW 16 */ 00837 }; 00838 static inline unsigned int DACx_Direct_Data_671x(int channel) 00839 { 00840 return channel; 00841 } 00842 enum AO_Misc_611x_Bits { 00843 CLEAR_WG = 1, 00844 }; 00845 enum cs5529_configuration_bits { 00846 CSCFG_CAL_CONTROL_MASK = 0x7, 00847 CSCFG_SELF_CAL_OFFSET = 0x1, 00848 CSCFG_SELF_CAL_GAIN = 0x2, 00849 CSCFG_SELF_CAL_OFFSET_GAIN = 0x3, 00850 CSCFG_SYSTEM_CAL_OFFSET = 0x5, 00851 CSCFG_SYSTEM_CAL_GAIN = 0x6, 00852 CSCFG_DONE = 1 << 3, 00853 CSCFG_POWER_SAVE_SELECT = 1 << 4, 00854 CSCFG_PORT_MODE = 1 << 5, 00855 CSCFG_RESET_VALID = 1 << 6, 00856 CSCFG_RESET = 1 << 7, 00857 CSCFG_UNIPOLAR = 1 << 12, 00858 CSCFG_WORD_RATE_2180_CYCLES = 0x0 << 13, 00859 CSCFG_WORD_RATE_1092_CYCLES = 0x1 << 13, 00860 CSCFG_WORD_RATE_532_CYCLES = 0x2 << 13, 00861 CSCFG_WORD_RATE_388_CYCLES = 0x3 << 13, 00862 CSCFG_WORD_RATE_324_CYCLES = 0x4 << 13, 00863 CSCFG_WORD_RATE_17444_CYCLES = 0x5 << 13, 00864 CSCFG_WORD_RATE_8724_CYCLES = 0x6 << 13, 00865 CSCFG_WORD_RATE_4364_CYCLES = 0x7 << 13, 00866 CSCFG_WORD_RATE_MASK = 0x7 << 13, 00867 CSCFG_LOW_POWER = 1 << 16, 00868 }; 00869 static inline unsigned int CS5529_CONFIG_DOUT(int output) 00870 { 00871 return 1 << (18 + output); 00872 } 00873 static inline unsigned int CS5529_CONFIG_AOUT(int output) 00874 { 00875 return 1 << (22 + output); 00876 } 00877 enum cs5529_command_bits { 00878 CSCMD_POWER_SAVE = 0x1, 00879 CSCMD_REGISTER_SELECT_MASK = 0xe, 00880 CSCMD_OFFSET_REGISTER = 0x0, 00881 CSCMD_GAIN_REGISTER = 0x2, 00882 CSCMD_CONFIG_REGISTER = 0x4, 00883 CSCMD_READ = 0x10, 00884 CSCMD_CONTINUOUS_CONVERSIONS = 0x20, 00885 CSCMD_SINGLE_CONVERSION = 0x40, 00886 CSCMD_COMMAND = 0x80, 00887 }; 00888 enum cs5529_status_bits { 00889 CSS_ADC_BUSY = 0x1, 00890 CSS_OSC_DETECT = 0x2, /* indicates adc error */ 00891 CSS_OVERRANGE = 0x4, 00892 }; 00893 #define SerDacLd(x) (0x08<<(x)) 00894 00895 /* 00896 This is stuff unique to the NI E series drivers, 00897 but I thought I'd put it here anyway. 00898 */ 00899 00900 enum { ai_gain_16 = 00901 0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x, ai_gain_622x, 00902 ai_gain_628x, ai_gain_6143 }; 00903 enum caldac_enum { caldac_none = 0, mb88341, dac8800, dac8043, ad8522, 00904 ad8804, ad8842, ad8804_debug 00905 }; 00906 enum ni_reg_type { 00907 ni_reg_normal = 0x0, 00908 ni_reg_611x = 0x1, 00909 ni_reg_6711 = 0x2, 00910 ni_reg_6713 = 0x4, 00911 ni_reg_67xx_mask = 0x6, 00912 ni_reg_6xxx_mask = 0x7, 00913 ni_reg_622x = 0x8, 00914 ni_reg_625x = 0x10, 00915 ni_reg_628x = 0x18, 00916 ni_reg_m_series_mask = 0x18, 00917 ni_reg_6143 = 0x20 00918 }; 00919 00920 static const comedi_lrange range_ni_E_ao_ext; 00921 00922 enum m_series_register_offsets { 00923 M_Offset_CDIO_DMA_Select = 0x7, // write 00924 M_Offset_SCXI_Status = 0x7, // read 00925 M_Offset_AI_AO_Select = 0x9, // write, same offset as e-series 00926 M_Offset_SCXI_Serial_Data_In = 0x9, // read 00927 M_Offset_G0_G1_Select = 0xb, // write, same offset as e-series 00928 M_Offset_Misc_Command = 0xf, 00929 M_Offset_SCXI_Serial_Data_Out = 0x11, 00930 M_Offset_SCXI_Control = 0x13, 00931 M_Offset_SCXI_Output_Enable = 0x15, 00932 M_Offset_AI_FIFO_Data = 0x1c, 00933 M_Offset_Static_Digital_Output = 0x24, // write 00934 M_Offset_Static_Digital_Input = 0x24, // read 00935 M_Offset_DIO_Direction = 0x28, 00936 M_Offset_Cal_PWM = 0x40, 00937 M_Offset_AI_Config_FIFO_Data = 0x5e, 00938 M_Offset_Interrupt_C_Enable = 0x88, // write 00939 M_Offset_Interrupt_C_Status = 0x88, // read 00940 M_Offset_Analog_Trigger_Control = 0x8c, 00941 M_Offset_AO_Serial_Interrupt_Enable = 0xa0, 00942 M_Offset_AO_Serial_Interrupt_Ack = 0xa1, // write 00943 M_Offset_AO_Serial_Interrupt_Status = 0xa1, // read 00944 M_Offset_AO_Calibration = 0xa3, 00945 M_Offset_AO_FIFO_Data = 0xa4, 00946 M_Offset_PFI_Filter = 0xb0, 00947 M_Offset_RTSI_Filter = 0xb4, 00948 M_Offset_SCXI_Legacy_Compatibility = 0xbc, 00949 M_Offset_Interrupt_A_Ack = 0x104, // write 00950 M_Offset_AI_Status_1 = 0x104, // read 00951 M_Offset_Interrupt_B_Ack = 0x106, // write 00952 M_Offset_AO_Status_1 = 0x106, // read 00953 M_Offset_AI_Command_2 = 0x108, // write 00954 M_Offset_G01_Status = 0x108, // read 00955 M_Offset_AO_Command_2 = 0x10a, 00956 M_Offset_AO_Status_2 = 0x10c, // read 00957 M_Offset_G0_Command = 0x10c, // write 00958 M_Offset_G1_Command = 0x10e, // write 00959 M_Offset_G0_HW_Save = 0x110, 00960 M_Offset_G0_HW_Save_High = 0x110, 00961 M_Offset_AI_Command_1 = 0x110, 00962 M_Offset_G0_HW_Save_Low = 0x112, 00963 M_Offset_AO_Command_1 = 0x112, 00964 M_Offset_G1_HW_Save = 0x114, 00965 M_Offset_G1_HW_Save_High = 0x114, 00966 M_Offset_G1_HW_Save_Low = 0x116, 00967 M_Offset_AI_Mode_1 = 0x118, 00968 M_Offset_G0_Save = 0x118, 00969 M_Offset_G0_Save_High = 0x118, 00970 M_Offset_AI_Mode_2 = 0x11a, 00971 M_Offset_G0_Save_Low = 0x11a, 00972 M_Offset_AI_SI_Load_A = 0x11c, 00973 M_Offset_G1_Save = 0x11c, 00974 M_Offset_G1_Save_High = 0x11c, 00975 M_Offset_G1_Save_Low = 0x11e, 00976 M_Offset_AI_SI_Load_B = 0x120, // write 00977 M_Offset_AO_UI_Save = 0x120, // read 00978 M_Offset_AI_SC_Load_A = 0x124, // write 00979 M_Offset_AO_BC_Save = 0x124, // read 00980 M_Offset_AI_SC_Load_B = 0x128, // write 00981 M_Offset_AO_UC_Save = 0x128, //read 00982 M_Offset_AI_SI2_Load_A = 0x12c, 00983 M_Offset_AI_SI2_Load_B = 0x130, 00984 M_Offset_G0_Mode = 0x134, 00985 M_Offset_G1_Mode = 0x136, // write 00986 M_Offset_Joint_Status_1 = 0x136, // read 00987 M_Offset_G0_Load_A = 0x138, 00988 M_Offset_Joint_Status_2 = 0x13a, 00989 M_Offset_G0_Load_B = 0x13c, 00990 M_Offset_G1_Load_A = 0x140, 00991 M_Offset_G1_Load_B = 0x144, 00992 M_Offset_G0_Input_Select = 0x148, 00993 M_Offset_G1_Input_Select = 0x14a, 00994 M_Offset_AO_Mode_1 = 0x14c, 00995 M_Offset_AO_Mode_2 = 0x14e, 00996 M_Offset_AO_UI_Load_A = 0x150, 00997 M_Offset_AO_UI_Load_B = 0x154, 00998 M_Offset_AO_BC_Load_A = 0x158, 00999 M_Offset_AO_BC_Load_B = 0x15c, 01000 M_Offset_AO_UC_Load_A = 0x160, 01001 M_Offset_AO_UC_Load_B = 0x164, 01002 M_Offset_Clock_and_FOUT = 0x170, 01003 M_Offset_IO_Bidirection_Pin = 0x172, 01004 M_Offset_RTSI_Trig_Direction = 0x174, 01005 M_Offset_Interrupt_Control = 0x176, 01006 M_Offset_AI_Output_Control = 0x178, 01007 M_Offset_Analog_Trigger_Etc = 0x17a, 01008 M_Offset_AI_START_STOP_Select = 0x17c, 01009 M_Offset_AI_Trigger_Select = 0x17e, 01010 M_Offset_AI_SI_Save = 0x180, // read 01011 M_Offset_AI_DIV_Load_A = 0x180, // write 01012 M_Offset_AI_SC_Save = 0x184, // read 01013 M_Offset_AO_Start_Select = 0x184, // write 01014 M_Offset_AO_Trigger_Select = 0x186, 01015 M_Offset_AO_Mode_3 = 0x18c, 01016 M_Offset_G0_Autoincrement = 0x188, 01017 M_Offset_G1_Autoincrement = 0x18a, 01018 M_Offset_Joint_Reset = 0x190, 01019 M_Offset_Interrupt_A_Enable = 0x192, 01020 M_Offset_Interrupt_B_Enable = 0x196, 01021 M_Offset_AI_Personal = 0x19a, 01022 M_Offset_AO_Personal = 0x19c, 01023 M_Offset_RTSI_Trig_A_Output = 0x19e, 01024 M_Offset_RTSI_Trig_B_Output = 0x1a0, 01025 M_Offset_RTSI_Shared_MUX = 0x1a2, 01026 M_Offset_AO_Output_Control = 0x1ac, 01027 M_Offset_AI_Mode_3 = 0x1ae, 01028 M_Offset_Configuration_Memory_Clear = 0x1a4, 01029 M_Offset_AI_FIFO_Clear = 0x1a6, 01030 M_Offset_AO_FIFO_Clear = 0x1a8, 01031 M_Offset_G0_Counting_Mode = 0x1b0, 01032 M_Offset_G1_Counting_Mode = 0x1b2, 01033 M_Offset_G0_Second_Gate = 0x1b4, 01034 M_Offset_G1_Second_Gate = 0x1b6, 01035 M_Offset_G0_DMA_Config = 0x1b8, // write 01036 M_Offset_G0_DMA_Status = 0x1b8, // read 01037 M_Offset_G1_DMA_Config = 0x1ba, // write 01038 M_Offset_G1_DMA_Status = 0x1ba, // read 01039 M_Offset_G0_MSeries_ABZ = 0x1c0, 01040 M_Offset_G1_MSeries_ABZ = 0x1c2, 01041 M_Offset_Clock_and_Fout2 = 0x1c4, 01042 M_Offset_PLL_Control = 0x1c6, 01043 M_Offset_PLL_Status = 0x1c8, 01044 M_Offset_PFI_Output_Select_1 = 0x1d0, 01045 M_Offset_PFI_Output_Select_2 = 0x1d2, 01046 M_Offset_PFI_Output_Select_3 = 0x1d4, 01047 M_Offset_PFI_Output_Select_4 = 0x1d6, 01048 M_Offset_PFI_Output_Select_5 = 0x1d8, 01049 M_Offset_PFI_Output_Select_6 = 0x1da, 01050 M_Offset_PFI_DI = 0x1dc, 01051 M_Offset_PFI_DO = 0x1de, 01052 M_Offset_AI_Config_FIFO_Bypass = 0x218, 01053 M_Offset_SCXI_DIO_Enable = 0x21c, 01054 M_Offset_CDI_FIFO_Data = 0x220, // read 01055 M_Offset_CDO_FIFO_Data = 0x220, // write 01056 M_Offset_CDIO_Status = 0x224, // read 01057 M_Offset_CDIO_Command = 0x224, // write 01058 M_Offset_CDI_Mode = 0x228, 01059 M_Offset_CDO_Mode = 0x22c, 01060 M_Offset_CDI_Mask_Enable = 0x230, 01061 M_Offset_CDO_Mask_Enable = 0x234, 01062 }; 01063 static inline int M_Offset_AO_Waveform_Order(int channel) 01064 { 01065 return 0xc2 + 0x4 * channel; 01066 }; 01067 static inline int M_Offset_AO_Config_Bank(int channel) 01068 { 01069 return 0xc3 + 0x4 * channel; 01070 }; 01071 static inline int M_Offset_DAC_Direct_Data(int channel) 01072 { 01073 return 0xc0 + 0x4 * channel; 01074 } 01075 static inline int M_Offset_Gen_PWM(int channel) 01076 { 01077 return 0x44 + 0x2 * channel; 01078 } 01079 static inline int M_Offset_Static_AI_Control(int i) 01080 { 01081 int offset[] = { 01082 0x64, 01083 0x261, 01084 0x262, 01085 0x263, 01086 }; 01087 if (((unsigned)i) >= sizeof(offset) / sizeof(offset[0])) { 01088 rt_printk("%s: invalid channel=%i\n", __FUNCTION__, i); 01089 return offset[0]; 01090 } 01091 return offset[i]; 01092 }; 01093 static inline int M_Offset_AO_Reference_Attenuation(int channel) 01094 { 01095 int offset[] = { 01096 0x264, 01097 0x265, 01098 0x266, 01099 0x267 01100 }; 01101 if (((unsigned)channel) >= sizeof(offset) / sizeof(offset[0])) { 01102 rt_printk("%s: invalid channel=%i\n", __FUNCTION__, channel); 01103 return offset[0]; 01104 } 01105 return offset[channel]; 01106 }; 01107 static inline unsigned M_Offset_PFI_Output_Select(unsigned n) 01108 { 01109 if (n < 1 || n > NUM_PFI_OUTPUT_SELECT_REGS) { 01110 rt_printk("%s: invalid pfi output select register=%i\n", 01111 __FUNCTION__, n); 01112 return M_Offset_PFI_Output_Select_1; 01113 } 01114 return M_Offset_PFI_Output_Select_1 + (n - 1) * 2; 01115 } 01116 01117 enum MSeries_AI_Config_FIFO_Data_Bits { 01118 MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6, 01119 MSeries_AI_Config_Channel_Type_Calibration_Bits = 0x0, 01120 MSeries_AI_Config_Channel_Type_Differential_Bits = 0x1 << 6, 01121 MSeries_AI_Config_Channel_Type_Common_Ref_Bits = 0x2 << 6, 01122 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits = 0x3 << 6, 01123 MSeries_AI_Config_Channel_Type_Aux_Bits = 0x5 << 6, 01124 MSeries_AI_Config_Channel_Type_Ghost_Bits = 0x7 << 6, 01125 MSeries_AI_Config_Polarity_Bit = 0x1000, // 0 for 2's complement encoding 01126 MSeries_AI_Config_Dither_Bit = 0x2000, 01127 MSeries_AI_Config_Last_Channel_Bit = 0x4000, 01128 }; 01129 static inline unsigned MSeries_AI_Config_Channel_Bits(unsigned channel) 01130 { 01131 return channel & 0xf; 01132 } 01133 static inline unsigned MSeries_AI_Config_Bank_Bits(enum ni_reg_type reg_type, 01134 unsigned channel) 01135 { 01136 unsigned bits = channel & 0x30; 01137 if (reg_type == ni_reg_622x) { 01138 if (channel & 0x40) 01139 bits |= 0x400; 01140 } 01141 return bits; 01142 } 01143 static inline unsigned MSeries_AI_Config_Gain_Bits(unsigned range) 01144 { 01145 return (range & 0x7) << 9; 01146 } 01147 01148 enum MSeries_Clock_and_Fout2_Bits { 01149 MSeries_PLL_In_Source_Select_RTSI0_Bits = 0xb, 01150 MSeries_PLL_In_Source_Select_Star_Trigger_Bits = 0x14, 01151 MSeries_PLL_In_Source_Select_RTSI7_Bits = 0x1b, 01152 MSeries_PLL_In_Source_Select_PXI_Clock10 = 0x1d, 01153 MSeries_PLL_In_Source_Select_Mask = 0x1f, 01154 MSeries_Timebase1_Select_Bit = 0x20, // use PLL for timebase 1 01155 MSeries_Timebase3_Select_Bit = 0x40, // use PLL for timebase 3 01156 /* use 10MHz instead of 20MHz for RTSI clock frequency. Appears 01157 to have no effect, at least on pxi-6281, which always uses 01158 20MHz rtsi clock frequency */ 01159 MSeries_RTSI_10MHz_Bit = 0x80 01160 }; 01161 static inline unsigned MSeries_PLL_In_Source_Select_RTSI_Bits(unsigned 01162 RTSI_channel) 01163 { 01164 if (RTSI_channel > 7) { 01165 rt_printk("%s: bug, invalid RTSI_channel=%i\n", __FUNCTION__, 01166 RTSI_channel); 01167 return 0; 01168 } 01169 if (RTSI_channel == 7) 01170 return MSeries_PLL_In_Source_Select_RTSI7_Bits; 01171 else 01172 return MSeries_PLL_In_Source_Select_RTSI0_Bits + RTSI_channel; 01173 } 01174 01175 enum MSeries_PLL_Control_Bits { 01176 MSeries_PLL_Enable_Bit = 0x1000, 01177 MSeries_PLL_VCO_Mode_200_325MHz_Bits = 0x0, 01178 MSeries_PLL_VCO_Mode_175_225MHz_Bits = 0x2000, 01179 MSeries_PLL_VCO_Mode_100_225MHz_Bits = 0x4000, 01180 MSeries_PLL_VCO_Mode_75_150MHz_Bits = 0x6000, 01181 }; 01182 static inline unsigned MSeries_PLL_Divisor_Bits(unsigned divisor) 01183 { 01184 static const unsigned max_divisor = 0x10; 01185 if (divisor < 1 || divisor > max_divisor) { 01186 rt_printk("%s: bug, invalid divisor=%i\n", __FUNCTION__, 01187 divisor); 01188 return 0; 01189 } 01190 return (divisor & 0xf) << 8; 01191 } 01192 static inline unsigned MSeries_PLL_Multiplier_Bits(unsigned multiplier) 01193 { 01194 static const unsigned max_multiplier = 0x100; 01195 if (multiplier < 1 || multiplier > max_multiplier) { 01196 rt_printk("%s: bug, invalid multiplier=%i\n", __FUNCTION__, 01197 multiplier); 01198 return 0; 01199 } 01200 return multiplier & 0xff; 01201 } 01202 01203 enum MSeries_PLL_Status { 01204 MSeries_PLL_Locked_Bit = 0x1 01205 }; 01206 01207 enum MSeries_AI_Config_FIFO_Bypass_Bits { 01208 MSeries_AI_Bypass_Channel_Mask = 0x7, 01209 MSeries_AI_Bypass_Bank_Mask = 0x78, 01210 MSeries_AI_Bypass_Cal_Sel_Pos_Mask = 0x380, 01211 MSeries_AI_Bypass_Cal_Sel_Neg_Mask = 0x1c00, 01212 MSeries_AI_Bypass_Mode_Mux_Mask = 0x6000, 01213 MSeries_AO_Bypass_AO_Cal_Sel_Mask = 0x38000, 01214 MSeries_AI_Bypass_Gain_Mask = 0x1c0000, 01215 MSeries_AI_Bypass_Dither_Bit = 0x200000, 01216 MSeries_AI_Bypass_Polarity_Bit = 0x400000, // 0 for 2's complement encoding 01217 MSeries_AI_Bypass_Config_FIFO_Bit = 0x80000000 01218 }; 01219 static inline unsigned MSeries_AI_Bypass_Cal_Sel_Pos_Bits(int 01220 calibration_source) 01221 { 01222 return (calibration_source << 7) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask; 01223 } 01224 static inline unsigned MSeries_AI_Bypass_Cal_Sel_Neg_Bits(int 01225 calibration_source) 01226 { 01227 return (calibration_source << 10) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask; 01228 } 01229 static inline unsigned MSeries_AI_Bypass_Gain_Bits(int gain) 01230 { 01231 return (gain << 18) & MSeries_AI_Bypass_Gain_Mask; 01232 } 01233 01234 enum MSeries_AO_Config_Bank_Bits { 01235 MSeries_AO_DAC_Offset_Select_Mask = 0x7, 01236 MSeries_AO_DAC_Offset_0V_Bits = 0x0, 01237 MSeries_AO_DAC_Offset_5V_Bits = 0x1, 01238 MSeries_AO_DAC_Reference_Mask = 0x38, 01239 MSeries_AO_DAC_Reference_10V_Internal_Bits = 0x0, 01240 MSeries_AO_DAC_Reference_5V_Internal_Bits = 0x8, 01241 MSeries_AO_Update_Timed_Bit = 0x40, 01242 MSeries_AO_Bipolar_Bit = 0x80 // turns on 2's complement encoding 01243 }; 01244 01245 enum MSeries_AO_Reference_Attenuation_Bits { 01246 MSeries_Attenuate_x5_Bit = 0x1 01247 }; 01248 01249 static inline unsigned MSeries_Cal_PWM_High_Time_Bits(unsigned count) 01250 { 01251 return (count << 16) & 0xffff0000; 01252 } 01253 01254 static inline unsigned MSeries_Cal_PWM_Low_Time_Bits(unsigned count) 01255 { 01256 return count & 0xffff; 01257 } 01258 01259 static inline unsigned MSeries_PFI_Output_Select_Mask(unsigned channel) 01260 { 01261 return 0x1f << (channel % 3) * 5; 01262 }; 01263 static inline unsigned MSeries_PFI_Output_Select_Bits(unsigned channel, 01264 unsigned source) 01265 { 01266 return (source & 0x1f) << ((channel % 3) * 5); 01267 }; 01268 01269 // inverse to MSeries_PFI_Output_Select_Bits 01270 static inline unsigned MSeries_PFI_Output_Select_Source(unsigned channel, 01271 unsigned bits) 01272 { 01273 return (bits >> ((channel % 3) * 5)) & 0x1f; 01274 }; 01275 01276 enum MSeries_Gi_DMA_Config_Bits { 01277 Gi_DMA_BankSW_Error_Bit = 0x10, 01278 Gi_DMA_Reset_Bit = 0x8, 01279 Gi_DMA_Int_Enable_Bit = 0x4, 01280 Gi_DMA_Write_Bit = 0x2, 01281 Gi_DMA_Enable_Bit = 0x1, 01282 }; 01283 01284 static inline unsigned MSeries_PFI_Filter_Select_Mask(unsigned channel) 01285 { 01286 return 0x3 << (channel * 2); 01287 } 01288 static inline unsigned MSeries_PFI_Filter_Select_Bits(unsigned channel, 01289 unsigned filter) 01290 { 01291 return (filter << (channel * 01292 2)) & MSeries_PFI_Filter_Select_Mask(channel); 01293 } 01294 01295 enum CDIO_DMA_Select_Bits { 01296 CDI_DMA_Select_Shift = 0, 01297 CDI_DMA_Select_Mask = 0xf, 01298 CDO_DMA_Select_Shift = 4, 01299 CDO_DMA_Select_Mask = 0xf << CDO_DMA_Select_Shift 01300 }; 01301 01302 enum CDIO_Status_Bits { 01303 CDO_FIFO_Empty_Bit = 0x1, 01304 CDO_FIFO_Full_Bit = 0x2, 01305 CDO_FIFO_Request_Bit = 0x4, 01306 CDO_Overrun_Bit = 0x8, 01307 CDO_Underflow_Bit = 0x10, 01308 CDI_FIFO_Empty_Bit = 0x10000, 01309 CDI_FIFO_Full_Bit = 0x20000, 01310 CDI_FIFO_Request_Bit = 0x40000, 01311 CDI_Overrun_Bit = 0x80000, 01312 CDI_Overflow_Bit = 0x100000 01313 }; 01314 01315 enum CDIO_Command_Bits { 01316 CDO_Disarm_Bit = 0x1, 01317 CDO_Arm_Bit = 0x2, 01318 CDI_Disarm_Bit = 0x4, 01319 CDI_Arm_Bit = 0x8, 01320 CDO_Reset_Bit = 0x10, 01321 CDI_Reset_Bit = 0x20, 01322 CDO_Error_Interrupt_Enable_Set_Bit = 0x40, 01323 CDO_Error_Interrupt_Enable_Clear_Bit = 0x80, 01324 CDI_Error_Interrupt_Enable_Set_Bit = 0x100, 01325 CDI_Error_Interrupt_Enable_Clear_Bit = 0x200, 01326 CDO_FIFO_Request_Interrupt_Enable_Set_Bit = 0x400, 01327 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x800, 01328 CDI_FIFO_Request_Interrupt_Enable_Set_Bit = 0x1000, 01329 CDI_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x2000, 01330 CDO_Error_Interrupt_Confirm_Bit = 0x4000, 01331 CDI_Error_Interrupt_Confirm_Bit = 0x8000, 01332 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit = 0x10000, 01333 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit = 0x20000, 01334 CDO_SW_Update_Bit = 0x80000, 01335 CDI_SW_Update_Bit = 0x100000 01336 }; 01337 01338 enum CDI_Mode_Bits { 01339 CDI_Sample_Source_Select_Mask = 0x3f, 01340 CDI_Halt_On_Error_Bit = 0x200, 01341 CDI_Polarity_Bit = 0x400, // sample clock on falling edge 01342 CDI_FIFO_Mode_Bit = 0x800, // set for half full mode, clear for not empty mode 01343 CDI_Data_Lane_Mask = 0x3000, // data lanes specify which dio channels map to byte or word accesses to the dio fifos 01344 CDI_Data_Lane_0_15_Bits = 0x0, 01345 CDI_Data_Lane_16_31_Bits = 0x1000, 01346 CDI_Data_Lane_0_7_Bits = 0x0, 01347 CDI_Data_Lane_8_15_Bits = 0x1000, 01348 CDI_Data_Lane_16_23_Bits = 0x2000, 01349 CDI_Data_Lane_24_31_Bits = 0x3000 01350 }; 01351 01352 enum CDO_Mode_Bits { 01353 CDO_Sample_Source_Select_Mask = 0x3f, 01354 CDO_Retransmit_Bit = 0x100, 01355 CDO_Halt_On_Error_Bit = 0x200, 01356 CDO_Polarity_Bit = 0x400, // sample clock on falling edge 01357 CDO_FIFO_Mode_Bit = 0x800, // set for half full mode, clear for not full mode 01358 CDO_Data_Lane_Mask = 0x3000, // data lanes specify which dio channels map to byte or word accesses to the dio fifos 01359 CDO_Data_Lane_0_15_Bits = 0x0, 01360 CDO_Data_Lane_16_31_Bits = 0x1000, 01361 CDO_Data_Lane_0_7_Bits = 0x0, 01362 CDO_Data_Lane_8_15_Bits = 0x1000, 01363 CDO_Data_Lane_16_23_Bits = 0x2000, 01364 CDO_Data_Lane_24_31_Bits = 0x3000 01365 }; 01366 01367 enum Interrupt_C_Enable_Bits { 01368 Interrupt_Group_C_Enable_Bit = 0x1 01369 }; 01370 01371 enum Interrupt_C_Status_Bits { 01372 Interrupt_Group_C_Status_Bit = 0x1 01373 }; 01374 01375 #define M_SERIES_EEPROM_SIZE 1024 01376 01377 typedef struct ni_board_struct { 01378 int device_id; 01379 int isapnp_id; 01380 char *name; 01381 01382 int n_adchan; 01383 int adbits; 01384 01385 int ai_fifo_depth; 01386 unsigned int alwaysdither:1; 01387 int gainlkup; 01388 int ai_speed; 01389 01390 int n_aochan; 01391 int aobits; 01392 int ao_fifo_depth; 01393 const comedi_lrange *ao_range_table; 01394 unsigned ao_speed; 01395 01396 unsigned num_p0_dio_channels; 01397 01398 int reg_type; 01399 unsigned int ao_unipolar:1; 01400 unsigned int has_8255:1; 01401 unsigned int has_analog_trig:1; 01402 01403 enum caldac_enum caldac[3]; 01404 } ni_board; 01405 01406 #define n_ni_boards (sizeof(ni_boards)/sizeof(ni_board)) 01407 01408 #define boardtype (*(ni_board *)dev->board_ptr) 01409 01410 #define MAX_N_AO_CHAN 8 01411 #define NUM_GPCT 2 01412 01413 #define NI_PRIVATE_COMMON \ 01414 uint16_t (*stc_readw)(comedi_device *dev, int register); \ 01415 uint32_t (*stc_readl)(comedi_device *dev, int register); \ 01416 void (*stc_writew)(comedi_device *dev, uint16_t value, int register); \ 01417 void (*stc_writel)(comedi_device *dev, uint32_t value, int register); \ 01418 \ 01419 unsigned short dio_output; \ 01420 unsigned short dio_control; \ 01421 int ao0p,ao1p; \ 01422 int lastchan; \ 01423 int last_do; \ 01424 int rt_irq; \ 01425 int irqmask; \ 01426 int aimode; \ 01427 int ai_continuous; \ 01428 int blocksize; \ 01429 int n_left; \ 01430 unsigned int ai_calib_source; \ 01431 unsigned int ai_calib_source_enabled; \ 01432 spinlock_t window_lock; \ 01433 spinlock_t soft_reg_copy_lock; \ 01434 spinlock_t mite_channel_lock; \ 01435 \ 01436 int changain_state; \ 01437 unsigned int changain_spec; \ 01438 \ 01439 unsigned int caldac_maxdata_list[MAX_N_CALDACS]; \ 01440 unsigned short ao[MAX_N_AO_CHAN]; \ 01441 unsigned short caldacs[MAX_N_CALDACS]; \ 01442 \ 01443 unsigned short ai_cmd2; \ 01444 \ 01445 unsigned short ao_conf[MAX_N_AO_CHAN]; \ 01446 unsigned short ao_mode1; \ 01447 unsigned short ao_mode2; \ 01448 unsigned short ao_mode3; \ 01449 unsigned short ao_cmd1; \ 01450 unsigned short ao_cmd2; \ 01451 unsigned short ao_cmd3; \ 01452 unsigned short ao_trigger_select; \ 01453 \ 01454 struct ni_gpct_device *counter_dev; \ 01455 unsigned short an_trig_etc_reg; \ 01456 \ 01457 unsigned ai_offset[512]; \ 01458 \ 01459 unsigned long serial_interval_ns; \ 01460 unsigned char serial_hw_mode; \ 01461 unsigned short clock_and_fout; \ 01462 unsigned short clock_and_fout2; \ 01463 \ 01464 unsigned short int_a_enable_reg; \ 01465 unsigned short int_b_enable_reg; \ 01466 unsigned short io_bidirection_pin_reg; \ 01467 unsigned short rtsi_trig_direction_reg; \ 01468 unsigned short rtsi_trig_a_output_reg; \ 01469 unsigned short rtsi_trig_b_output_reg; \ 01470 unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS]; \ 01471 unsigned short ai_ao_select_reg; \ 01472 unsigned short g0_g1_select_reg; \ 01473 unsigned short cdio_dma_select_reg; \ 01474 \ 01475 unsigned clock_ns; \ 01476 unsigned clock_source; \ 01477 \ 01478 unsigned short atrig_mode; \ 01479 unsigned short atrig_high; \ 01480 unsigned short atrig_low; \ 01481 \ 01482 unsigned short pwm_up_count; \ 01483 unsigned short pwm_down_count; \ 01484 \ 01485 sampl_t ai_fifo_buffer[0x2000]; \ 01486 uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE]; \ 01487 uint32_t serial_number; \ 01488 \ 01489 struct mite_struct *mite; \ 01490 struct mite_channel *ai_mite_chan; \ 01491 struct mite_channel *ao_mite_chan;\ 01492 struct mite_channel *cdo_mite_chan;\ 01493 struct mite_dma_descriptor_ring *ai_mite_ring; \ 01494 struct mite_dma_descriptor_ring *ao_mite_ring; \ 01495 struct mite_dma_descriptor_ring *cdo_mite_ring; \ 01496 struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT]; 01497 01498 #endif /* _COMEDI_NI_STC_H */
1.7.4 
