Classes |
| struct | NI_660xRegisterData |
| struct | ni_660x_board |
| struct | ni_660x_private |
Defines |
| #define | NUM_PFI_CHANNELS 40 |
| #define | MAX_DMA_CHANNEL 4 |
| #define | NI_660X_MAX_NUM_CHIPS 2 |
| #define | NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip) |
| #define | n_ni_660x_boards (sizeof(ni_660x_boards)/sizeof(ni_660x_boards[0])) |
Enumerations |
| enum | ni_660x_constants { min_counter_pfi_chan = 8,
max_dio_pfi_chan = 31,
counters_per_chip = 4
} |
| enum | NI_660x_Register {
G0InterruptAcknowledge,
G0StatusRegister,
G1InterruptAcknowledge,
G1StatusRegister,
G01StatusRegister,
G0CommandRegister,
STCDIOParallelInput,
G1CommandRegister,
G0HWSaveRegister,
G1HWSaveRegister,
STCDIOOutput,
STCDIOControl,
G0SWSaveRegister,
G1SWSaveRegister,
G0ModeRegister,
G01JointStatus1Register,
G1ModeRegister,
STCDIOSerialInput,
G0LoadARegister,
G01JointStatus2Register,
G0LoadBRegister,
G1LoadARegister,
G1LoadBRegister,
G0InputSelectRegister,
G1InputSelectRegister,
G0AutoincrementRegister,
G1AutoincrementRegister,
G01JointResetRegister,
G0InterruptEnable,
G1InterruptEnable,
G0CountingModeRegister,
G1CountingModeRegister,
G0SecondGateRegister,
G1SecondGateRegister,
G0DMAConfigRegister,
G0DMAStatusRegister,
G1DMAConfigRegister,
G1DMAStatusRegister,
G2InterruptAcknowledge,
G2StatusRegister,
G3InterruptAcknowledge,
G3StatusRegister,
G23StatusRegister,
G2CommandRegister,
G3CommandRegister,
G2HWSaveRegister,
G3HWSaveRegister,
G2SWSaveRegister,
G3SWSaveRegister,
G2ModeRegister,
G23JointStatus1Register,
G3ModeRegister,
G2LoadARegister,
G23JointStatus2Register,
G2LoadBRegister,
G3LoadARegister,
G3LoadBRegister,
G2InputSelectRegister,
G3InputSelectRegister,
G2AutoincrementRegister,
G3AutoincrementRegister,
G23JointResetRegister,
G2InterruptEnable,
G3InterruptEnable,
G2CountingModeRegister,
G3CountingModeRegister,
G3SecondGateRegister,
G2SecondGateRegister,
G2DMAConfigRegister,
G2DMAStatusRegister,
G3DMAConfigRegister,
G3DMAStatusRegister,
DIO32Input,
DIO32Output,
ClockConfigRegister,
GlobalInterruptStatusRegister,
DMAConfigRegister,
GlobalInterruptConfigRegister,
IOConfigReg0_1,
IOConfigReg2_3,
IOConfigReg4_5,
IOConfigReg6_7,
IOConfigReg8_9,
IOConfigReg10_11,
IOConfigReg12_13,
IOConfigReg14_15,
IOConfigReg16_17,
IOConfigReg18_19,
IOConfigReg20_21,
IOConfigReg22_23,
IOConfigReg24_25,
IOConfigReg26_27,
IOConfigReg28_29,
IOConfigReg30_31,
IOConfigReg32_33,
IOConfigReg34_35,
IOConfigReg36_37,
IOConfigReg38_39,
NumRegisters
} |
| enum | ni_660x_register_width { DATA_1B,
DATA_2B,
DATA_4B
} |
| enum | ni_660x_register_direction { NI_660x_READ,
NI_660x_WRITE,
NI_660x_READ_WRITE
} |
| enum | ni_660x_pfi_output_select { pfi_output_select_high_Z = 0,
pfi_output_select_counter = 1,
pfi_output_select_do = 2,
num_pfi_output_selects
} |
| enum | ni_660x_subdevices { NI_660X_DIO_SUBDEV = 1,
NI_660X_GPCT_SUBDEV_0 = 2
} |
| enum | clock_config_register_bits { CounterSwap = 0x1 << 21
} |
| enum | dma_selection { dma_selection_none = 0x1f
} |
| enum | global_interrupt_status_register_bits {
Counter_0_Int_Bit = 0x100,
Counter_1_Int_Bit = 0x200,
Counter_2_Int_Bit = 0x400,
Counter_3_Int_Bit = 0x800,
Cascade_Int_Bit = 0x20000000,
Global_Int_Bit = 0x80000000
} |
| enum | global_interrupt_config_register_bits { Cascade_Int_Enable_Bit = 0x20000000,
Global_Int_Polarity_Bit = 0x40000000,
Global_Int_Enable_Bit = 0x80000000
} |
Functions |
| | MODULE_DEVICE_TABLE (pci, ni_660x_pci_table) |
| | COMEDI_PCI_INITCLEANUP (driver_ni_660x, ni_660x_pci_table) |
| void | ni_660x_release_mite_channel (comedi_device *dev, struct ni_gpct *counter) |
1.7.4 
