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RTXI 1.3
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RTXI 1.3
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00001 /* 00002 me4000.h 00003 Register descriptions and defines for the ME-4000 board family 00004 00005 COMEDI - Linux Control and Measurement Device Interface 00006 Copyright (C) 1998-9 David A. Schleef <ds@schleef.org> 00007 00008 This program is free software; you can redistribute it and/or modify 00009 it under the terms of the GNU General Public License as published by 00010 the Free Software Foundation; either version 2 of the License, or 00011 (at your option) any later version. 00012 00013 This program is distributed in the hope that it will be useful, 00014 but WITHOUT ANY WARRANTY; without even the implied warranty of 00015 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00016 GNU General Public License for more details. 00017 00018 You should have received a copy of the GNU General Public License 00019 along with this program; if not, write to the Free Software 00020 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 00021 00022 */ 00023 00024 #ifndef _ME4000_H_ 00025 #define _ME4000_H_ 00026 00027 /*============================================================================= 00028 Debug section 00029 ===========================================================================*/ 00030 00031 #undef ME4000_CALL_DEBUG // Debug function entry and exit 00032 #undef ME4000_PORT_DEBUG // Debug port access 00033 #undef ME4000_ISR_DEBUG // Debug the interrupt service routine 00034 #undef ME4000_DEBUG // General purpose debug masseges 00035 00036 #ifdef ME4000_CALL_DEBUG 00037 #undef CALL_PDEBUG 00038 #define CALL_PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args) 00039 #else 00040 # define CALL_PDEBUG(fmt, args...) // no debugging, do nothing 00041 #endif 00042 00043 #ifdef ME4000_PORT_DEBUG 00044 #undef PORT_PDEBUG 00045 #define PORT_PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args) 00046 #else 00047 #define PORT_PDEBUG(fmt, args...) // no debugging, do nothing 00048 #endif 00049 00050 #ifdef ME4000_ISR_DEBUG 00051 #undef ISR_PDEBUG 00052 #define ISR_PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args) 00053 #else 00054 #define ISR_PDEBUG(fmt, args...) // no debugging, do nothing 00055 #endif 00056 00057 #ifdef ME4000_DEBUG 00058 #undef PDEBUG 00059 #define PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args) 00060 #else 00061 #define PDEBUG(fmt, args...) // no debugging, do nothing 00062 #endif 00063 00064 /*============================================================================= 00065 PCI vendor and device IDs 00066 ===========================================================================*/ 00067 00068 #define PCI_VENDOR_ID_MEILHAUS 0x1402 00069 00070 #define PCI_DEVICE_ID_MEILHAUS_ME4650 0x4650 // Low Cost version 00071 00072 #define PCI_DEVICE_ID_MEILHAUS_ME4660 0x4660 // Standard version 00073 #define PCI_DEVICE_ID_MEILHAUS_ME4660I 0x4661 // Isolated version 00074 #define PCI_DEVICE_ID_MEILHAUS_ME4660S 0x4662 // Standard version with Sample and Hold 00075 #define PCI_DEVICE_ID_MEILHAUS_ME4660IS 0x4663 // Isolated version with Sample and Hold 00076 00077 #define PCI_DEVICE_ID_MEILHAUS_ME4670 0x4670 // Standard version 00078 #define PCI_DEVICE_ID_MEILHAUS_ME4670I 0x4671 // Isolated version 00079 #define PCI_DEVICE_ID_MEILHAUS_ME4670S 0x4672 // Standard version with Sample and Hold 00080 #define PCI_DEVICE_ID_MEILHAUS_ME4670IS 0x4673 // Isolated version with Sample and Hold 00081 00082 #define PCI_DEVICE_ID_MEILHAUS_ME4680 0x4680 // Standard version 00083 #define PCI_DEVICE_ID_MEILHAUS_ME4680I 0x4681 // Isolated version 00084 #define PCI_DEVICE_ID_MEILHAUS_ME4680S 0x4682 // Standard version with Sample and Hold 00085 #define PCI_DEVICE_ID_MEILHAUS_ME4680IS 0x4683 // Isolated version with Sample and Hold 00086 00087 /*============================================================================= 00088 ME-4000 base register offsets 00089 ===========================================================================*/ 00090 00091 #define ME4000_AO_00_CTRL_REG 0x00 // R/W 00092 #define ME4000_AO_00_STATUS_REG 0x04 // R/_ 00093 #define ME4000_AO_00_FIFO_REG 0x08 // _/W 00094 #define ME4000_AO_00_SINGLE_REG 0x0C // R/W 00095 #define ME4000_AO_00_TIMER_REG 0x10 // _/W 00096 00097 #define ME4000_AO_01_CTRL_REG 0x18 // R/W 00098 #define ME4000_AO_01_STATUS_REG 0x1C // R/_ 00099 #define ME4000_AO_01_FIFO_REG 0x20 // _/W 00100 #define ME4000_AO_01_SINGLE_REG 0x24 // R/W 00101 #define ME4000_AO_01_TIMER_REG 0x28 // _/W 00102 00103 #define ME4000_AO_02_CTRL_REG 0x30 // R/W 00104 #define ME4000_AO_02_STATUS_REG 0x34 // R/_ 00105 #define ME4000_AO_02_FIFO_REG 0x38 // _/W 00106 #define ME4000_AO_02_SINGLE_REG 0x3C // R/W 00107 #define ME4000_AO_02_TIMER_REG 0x40 // _/W 00108 00109 #define ME4000_AO_03_CTRL_REG 0x48 // R/W 00110 #define ME4000_AO_03_STATUS_REG 0x4C // R/_ 00111 #define ME4000_AO_03_FIFO_REG 0x50 // _/W 00112 #define ME4000_AO_03_SINGLE_REG 0x54 // R/W 00113 #define ME4000_AO_03_TIMER_REG 0x58 // _/W 00114 00115 #define ME4000_AI_CTRL_REG 0x74 // _/W 00116 #define ME4000_AI_STATUS_REG 0x74 // R/_ 00117 #define ME4000_AI_CHANNEL_LIST_REG 0x78 // _/W 00118 #define ME4000_AI_DATA_REG 0x7C // R/_ 00119 #define ME4000_AI_CHAN_TIMER_REG 0x80 // _/W 00120 #define ME4000_AI_CHAN_PRE_TIMER_REG 0x84 // _/W 00121 #define ME4000_AI_SCAN_TIMER_LOW_REG 0x88 // _/W 00122 #define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8C // _/W 00123 #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90 // _/W 00124 #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94 // _/W 00125 #define ME4000_AI_START_REG 0x98 // R/_ 00126 00127 #define ME4000_IRQ_STATUS_REG 0x9C // R/_ 00128 00129 #define ME4000_DIO_PORT_0_REG 0xA0 // R/W 00130 #define ME4000_DIO_PORT_1_REG 0xA4 // R/W 00131 #define ME4000_DIO_PORT_2_REG 0xA8 // R/W 00132 #define ME4000_DIO_PORT_3_REG 0xAC // R/W 00133 #define ME4000_DIO_DIR_REG 0xB0 // R/W 00134 00135 #define ME4000_AO_LOADSETREG_XX 0xB4 // R/W 00136 00137 #define ME4000_DIO_CTRL_REG 0xB8 // R/W 00138 00139 #define ME4000_AO_DEMUX_ADJUST_REG 0xBC // -/W 00140 00141 #define ME4000_AI_SAMPLE_COUNTER_REG 0xC0 // _/W 00142 00143 /*============================================================================= 00144 Value to adjust Demux 00145 ===========================================================================*/ 00146 00147 #define ME4000_AO_DEMUX_ADJUST_VALUE 0x4C 00148 00149 /*============================================================================= 00150 Counter base register offsets 00151 ===========================================================================*/ 00152 00153 #define ME4000_CNT_COUNTER_0_REG 0x00 00154 #define ME4000_CNT_COUNTER_1_REG 0x01 00155 #define ME4000_CNT_COUNTER_2_REG 0x02 00156 #define ME4000_CNT_CTRL_REG 0x03 00157 00158 /*============================================================================= 00159 PLX base register offsets 00160 ===========================================================================*/ 00161 00162 #define PLX_INTCSR 0x4C // Interrupt control and status register 00163 #define PLX_ICR 0x50 // Initialization control register 00164 00165 /*============================================================================= 00166 Bits for the PLX_ICSR register 00167 ===========================================================================*/ 00168 00169 #define PLX_INTCSR_LOCAL_INT1_EN 0x01 // If set, local interrupt 1 is enabled (r/w) 00170 #define PLX_INTCSR_LOCAL_INT1_POL 0x02 // If set, local interrupt 1 polarity is active high (r/w) 00171 #define PLX_INTCSR_LOCAL_INT1_STATE 0x04 // If set, local interrupt 1 is active (r/_) 00172 #define PLX_INTCSR_LOCAL_INT2_EN 0x08 // If set, local interrupt 2 is enabled (r/w) 00173 #define PLX_INTCSR_LOCAL_INT2_POL 0x10 // If set, local interrupt 2 polarity is active high (r/w) 00174 #define PLX_INTCSR_LOCAL_INT2_STATE 0x20 // If set, local interrupt 2 is active (r/_) 00175 #define PLX_INTCSR_PCI_INT_EN 0x40 // If set, PCI interrupt is enabled (r/w) 00176 #define PLX_INTCSR_SOFT_INT 0x80 // If set, a software interrupt is generated (r/w) 00177 00178 /*============================================================================= 00179 Bits for the PLX_ICR register 00180 ===========================================================================*/ 00181 00182 #define PLX_ICR_BIT_EEPROM_CLOCK_SET 0x01000000 00183 #define PLX_ICR_BIT_EEPROM_CHIP_SELECT 0x02000000 00184 #define PLX_ICR_BIT_EEPROM_WRITE 0x04000000 00185 #define PLX_ICR_BIT_EEPROM_READ 0x08000000 00186 #define PLX_ICR_BIT_EEPROM_VALID 0x10000000 00187 00188 #define PLX_ICR_MASK_EEPROM 0x1F000000 00189 00190 #define EEPROM_DELAY 1 00191 00192 /*============================================================================= 00193 Bits for the ME4000_AO_CTRL_REG register 00194 ===========================================================================*/ 00195 00196 #define ME4000_AO_CTRL_BIT_MODE_0 0x001 00197 #define ME4000_AO_CTRL_BIT_MODE_1 0x002 00198 #define ME4000_AO_CTRL_MASK_MODE 0x003 00199 #define ME4000_AO_CTRL_BIT_STOP 0x004 00200 #define ME4000_AO_CTRL_BIT_ENABLE_FIFO 0x008 00201 #define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG 0x010 00202 #define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE 0x020 00203 #define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP 0x080 00204 #define ME4000_AO_CTRL_BIT_ENABLE_DO 0x100 00205 #define ME4000_AO_CTRL_BIT_ENABLE_IRQ 0x200 00206 #define ME4000_AO_CTRL_BIT_RESET_IRQ 0x400 00207 00208 /*============================================================================= 00209 Bits for the ME4000_AO_STATUS_REG register 00210 ===========================================================================*/ 00211 00212 #define ME4000_AO_STATUS_BIT_FSM 0x01 00213 #define ME4000_AO_STATUS_BIT_FF 0x02 00214 #define ME4000_AO_STATUS_BIT_HF 0x04 00215 #define ME4000_AO_STATUS_BIT_EF 0x08 00216 00217 /*============================================================================= 00218 Bits for the ME4000_AI_CTRL_REG register 00219 ===========================================================================*/ 00220 00221 #define ME4000_AI_CTRL_BIT_MODE_0 0x00000001 00222 #define ME4000_AI_CTRL_BIT_MODE_1 0x00000002 00223 #define ME4000_AI_CTRL_BIT_MODE_2 0x00000004 00224 #define ME4000_AI_CTRL_BIT_SAMPLE_HOLD 0x00000008 00225 #define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP 0x00000010 00226 #define ME4000_AI_CTRL_BIT_STOP 0x00000020 00227 #define ME4000_AI_CTRL_BIT_CHANNEL_FIFO 0x00000040 00228 #define ME4000_AI_CTRL_BIT_DATA_FIFO 0x00000080 00229 #define ME4000_AI_CTRL_BIT_FULLSCALE 0x00000100 00230 #define ME4000_AI_CTRL_BIT_OFFSET 0x00000200 00231 #define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG 0x00000400 00232 #define ME4000_AI_CTRL_BIT_EX_TRIG 0x00000800 00233 #define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING 0x00001000 00234 #define ME4000_AI_CTRL_BIT_EX_IRQ 0x00002000 00235 #define ME4000_AI_CTRL_BIT_EX_IRQ_RESET 0x00004000 00236 #define ME4000_AI_CTRL_BIT_LE_IRQ 0x00008000 00237 #define ME4000_AI_CTRL_BIT_LE_IRQ_RESET 0x00010000 00238 #define ME4000_AI_CTRL_BIT_HF_IRQ 0x00020000 00239 #define ME4000_AI_CTRL_BIT_HF_IRQ_RESET 0x00040000 00240 #define ME4000_AI_CTRL_BIT_SC_IRQ 0x00080000 00241 #define ME4000_AI_CTRL_BIT_SC_IRQ_RESET 0x00100000 00242 #define ME4000_AI_CTRL_BIT_SC_RELOAD 0x00200000 00243 #define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH 0x80000000 00244 00245 /*============================================================================= 00246 Bits for the ME4000_AI_STATUS_REG register 00247 ===========================================================================*/ 00248 00249 #define ME4000_AI_STATUS_BIT_EF_CHANNEL 0x00400000 00250 #define ME4000_AI_STATUS_BIT_HF_CHANNEL 0x00800000 00251 #define ME4000_AI_STATUS_BIT_FF_CHANNEL 0x01000000 00252 #define ME4000_AI_STATUS_BIT_EF_DATA 0x02000000 00253 #define ME4000_AI_STATUS_BIT_HF_DATA 0x04000000 00254 #define ME4000_AI_STATUS_BIT_FF_DATA 0x08000000 00255 #define ME4000_AI_STATUS_BIT_LE 0x10000000 00256 #define ME4000_AI_STATUS_BIT_FSM 0x20000000 00257 00258 /*============================================================================= 00259 Bits for the ME4000_IRQ_STATUS_REG register 00260 ===========================================================================*/ 00261 00262 #define ME4000_IRQ_STATUS_BIT_EX 0x01 00263 #define ME4000_IRQ_STATUS_BIT_LE 0x02 00264 #define ME4000_IRQ_STATUS_BIT_AI_HF 0x04 00265 #define ME4000_IRQ_STATUS_BIT_AO_0_HF 0x08 00266 #define ME4000_IRQ_STATUS_BIT_AO_1_HF 0x10 00267 #define ME4000_IRQ_STATUS_BIT_AO_2_HF 0x20 00268 #define ME4000_IRQ_STATUS_BIT_AO_3_HF 0x40 00269 #define ME4000_IRQ_STATUS_BIT_SC 0x80 00270 00271 /*============================================================================= 00272 Bits for the ME4000_DIO_CTRL_REG register 00273 ===========================================================================*/ 00274 00275 #define ME4000_DIO_CTRL_BIT_MODE_0 0x0001 00276 #define ME4000_DIO_CTRL_BIT_MODE_1 0x0002 00277 #define ME4000_DIO_CTRL_BIT_MODE_2 0x0004 00278 #define ME4000_DIO_CTRL_BIT_MODE_3 0x0008 00279 #define ME4000_DIO_CTRL_BIT_MODE_4 0x0010 00280 #define ME4000_DIO_CTRL_BIT_MODE_5 0x0020 00281 #define ME4000_DIO_CTRL_BIT_MODE_6 0x0040 00282 #define ME4000_DIO_CTRL_BIT_MODE_7 0x0080 00283 00284 #define ME4000_DIO_CTRL_BIT_FUNCTION_0 0x0100 00285 #define ME4000_DIO_CTRL_BIT_FUNCTION_1 0x0200 00286 00287 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 0x0400 00288 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 0x0800 00289 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 0x1000 00290 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 0x2000 00291 00292 /*============================================================================= 00293 Information about the hardware capabilities 00294 ===========================================================================*/ 00295 00296 typedef struct me4000_ao_info { 00297 int count; 00298 int fifo_count; 00299 } me4000_ao_info_t; 00300 00301 typedef struct me4000_ai_info { 00302 int count; 00303 int sh_count; 00304 int diff_count; 00305 int ex_trig_analog; 00306 } me4000_ai_info_t; 00307 00308 typedef struct me4000_dio_info { 00309 int count; 00310 } me4000_dio_info_t; 00311 00312 typedef struct me4000_cnt_info { 00313 int count; 00314 } me4000_cnt_info_t; 00315 00316 typedef struct me4000_board { 00317 const char *name; 00318 unsigned short device_id; 00319 me4000_ao_info_t ao; 00320 me4000_ai_info_t ai; 00321 me4000_dio_info_t dio; 00322 me4000_cnt_info_t cnt; 00323 } me4000_board_t; 00324 00325 #define thisboard ((const me4000_board_t *)dev->board_ptr) 00326 00327 /*============================================================================= 00328 Global board and subdevice information structures 00329 ===========================================================================*/ 00330 00331 typedef struct me4000_ao_context { 00332 int irq; 00333 00334 unsigned long mirror; // Store the last written value 00335 00336 unsigned long ctrl_reg; 00337 unsigned long status_reg; 00338 unsigned long fifo_reg; 00339 unsigned long single_reg; 00340 unsigned long timer_reg; 00341 unsigned long irq_status_reg; 00342 unsigned long preload_reg; 00343 } me4000_ao_context_t; 00344 00345 typedef struct me4000_ai_context { 00346 int irq; 00347 00348 unsigned long ctrl_reg; 00349 unsigned long status_reg; 00350 unsigned long channel_list_reg; 00351 unsigned long data_reg; 00352 unsigned long chan_timer_reg; 00353 unsigned long chan_pre_timer_reg; 00354 unsigned long scan_timer_low_reg; 00355 unsigned long scan_timer_high_reg; 00356 unsigned long scan_pre_timer_low_reg; 00357 unsigned long scan_pre_timer_high_reg; 00358 unsigned long start_reg; 00359 unsigned long irq_status_reg; 00360 unsigned long sample_counter_reg; 00361 } me4000_ai_context_t; 00362 00363 typedef struct me4000_dio_context { 00364 unsigned long dir_reg; 00365 unsigned long ctrl_reg; 00366 unsigned long port_0_reg; 00367 unsigned long port_1_reg; 00368 unsigned long port_2_reg; 00369 unsigned long port_3_reg; 00370 } me4000_dio_context_t; 00371 00372 typedef struct me4000_cnt_context { 00373 unsigned long ctrl_reg; 00374 unsigned long counter_0_reg; 00375 unsigned long counter_1_reg; 00376 unsigned long counter_2_reg; 00377 } me4000_cnt_context_t; 00378 00379 typedef struct me4000_info { 00380 unsigned long plx_regbase; // PLX configuration space base address 00381 unsigned long me4000_regbase; // Base address of the ME4000 00382 unsigned long timer_regbase; // Base address of the timer circuit 00383 unsigned long program_regbase; // Base address to set the program pin for the xilinx 00384 00385 unsigned long plx_regbase_size; // PLX register set space 00386 unsigned long me4000_regbase_size; // ME4000 register set space 00387 unsigned long timer_regbase_size; // Timer circuit register set space 00388 unsigned long program_regbase_size; // Size of program base address of the ME4000 00389 00390 unsigned int serial_no; // Serial number of the board 00391 unsigned char hw_revision; // Hardware revision of the board 00392 unsigned short vendor_id; // Meilhaus vendor id 00393 unsigned short device_id; // Device id 00394 00395 struct pci_dev *pci_dev_p; // General PCI information 00396 00397 unsigned int irq; // IRQ assigned from the PCI BIOS 00398 00399 struct me4000_ai_context ai_context; // Analog input specific context 00400 struct me4000_ao_context ao_context[4]; // Vector with analog output specific context 00401 struct me4000_dio_context dio_context; // Digital I/O specific context 00402 struct me4000_cnt_context cnt_context; // Counter specific context 00403 } me4000_info_t; 00404 00405 #define info ((me4000_info_t *)dev->private) 00406 00407 /*----------------------------------------------------------------------------- 00408 Defines for analog input 00409 ----------------------------------------------------------------------------*/ 00410 00411 /* General stuff */ 00412 #define ME4000_AI_FIFO_COUNT 2048 00413 00414 #define ME4000_AI_MIN_TICKS 66 00415 #define ME4000_AI_MIN_SAMPLE_TIME 2000 // Minimum sample time [ns] 00416 #define ME4000_AI_BASE_FREQUENCY (unsigned int) 33E6 00417 00418 /* Channel list defines and masks */ 00419 #define ME4000_AI_CHANNEL_LIST_COUNT 1024 00420 00421 #define ME4000_AI_LIST_INPUT_SINGLE_ENDED 0x000 00422 #define ME4000_AI_LIST_INPUT_DIFFERENTIAL 0x020 00423 00424 #define ME4000_AI_LIST_RANGE_BIPOLAR_10 0x000 00425 #define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 0x040 00426 #define ME4000_AI_LIST_RANGE_UNIPOLAR_10 0x080 00427 #define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 0x0C0 00428 00429 #define ME4000_AI_LIST_LAST_ENTRY 0x100 00430 00431 /*----------------------------------------------------------------------------- 00432 Defines for counters 00433 ----------------------------------------------------------------------------*/ 00434 00435 #define ME4000_CNT_COUNTER_0 0x00 00436 #define ME4000_CNT_COUNTER_1 0x40 00437 #define ME4000_CNT_COUNTER_2 0x80 00438 00439 #define ME4000_CNT_MODE_0 0x00 // Change state if zero crossing 00440 #define ME4000_CNT_MODE_1 0x02 // Retriggerable One-Shot 00441 #define ME4000_CNT_MODE_2 0x04 // Asymmetrical divider 00442 #define ME4000_CNT_MODE_3 0x06 // Symmetrical divider 00443 #define ME4000_CNT_MODE_4 0x08 // Counter start by software trigger 00444 #define ME4000_CNT_MODE_5 0x0A // Counter start by hardware trigger 00445 00446 #endif
1.7.4 
