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RTXI 1.3
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RTXI 1.3
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00001 /* 00002 include/comedi.h (installed as /usr/include/comedi.h) 00003 header file for comedi 00004 00005 COMEDI - Linux Control and Measurement Device Interface 00006 Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org> 00007 00008 This program is free software; you can redistribute it and/or modify 00009 it under the terms of the GNU Lesser General Public License as published by 00010 the Free Software Foundation; either version 2 of the License, or 00011 (at your option) any later version. 00012 00013 This program is distributed in the hope that it will be useful, 00014 but WITHOUT ANY WARRANTY; without even the implied warranty of 00015 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00016 GNU General Public License for more details. 00017 00018 You should have received a copy of the GNU General Public License 00019 along with this program; if not, write to the Free Software 00020 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 00021 00022 */ 00023 00024 #ifndef _COMEDI_H 00025 #define _COMEDI_H 00026 00027 #ifdef __cplusplus 00028 extern "C" { 00029 #endif 00030 00031 /* comedi's major device number */ 00032 #define COMEDI_MAJOR 98 00033 00034 /* 00035 maximum number of minor devices. This can be increased, although 00036 kernel structures are currently statically allocated, thus you 00037 don't want this to be much more than you actually use. 00038 */ 00039 #define COMEDI_NDEVICES 16 00040 00041 /* number of config options in the config structure */ 00042 #define COMEDI_NDEVCONFOPTS 32 00043 /*length of nth chunk of firmware data*/ 00044 #define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25 00045 #define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26 00046 #define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27 00047 #define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28 00048 #define COMEDI_DEVCONF_AUX_DATA_HI 29 /*most significant 32 bits of pointer address (if needed) */ 00049 #define COMEDI_DEVCONF_AUX_DATA_LO 30 /*least significant 32 bits of pointer address */ 00050 #define COMEDI_DEVCONF_AUX_DATA_LENGTH 31 /* total data length */ 00051 00052 /* max length of device and driver names */ 00053 #define COMEDI_NAMELEN 20 00054 00055 typedef unsigned int lsampl_t; 00056 typedef unsigned short sampl_t; 00057 00058 /* packs and unpacks a channel/range number */ 00059 00060 #define CR_PACK(chan,rng,aref) ( (((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan) ) 00061 #define CR_PACK_FLAGS(chan, range, aref, flags) (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK)) 00062 00063 #define CR_CHAN(a) ((a)&0xffff) 00064 #define CR_RANGE(a) (((a)>>16)&0xff) 00065 #define CR_AREF(a) (((a)>>24)&0x03) 00066 00067 #define CR_FLAGS_MASK 0xfc000000 00068 #define CR_ALT_FILTER (1<<26) 00069 #define CR_DITHER CR_ALT_FILTER 00070 #define CR_DEGLITCH CR_ALT_FILTER 00071 #define CR_ALT_SOURCE (1<<27) 00072 #define CR_EDGE (1<<30) 00073 #define CR_INVERT (1<<31) 00074 00075 #define AREF_GROUND 0x00 /* analog ref = analog ground */ 00076 #define AREF_COMMON 0x01 /* analog ref = analog common */ 00077 #define AREF_DIFF 0x02 /* analog ref = differential */ 00078 #define AREF_OTHER 0x03 /* analog ref = other (undefined) */ 00079 00080 /* counters -- these are arbitrary values */ 00081 #define GPCT_RESET 0x0001 00082 #define GPCT_SET_SOURCE 0x0002 00083 #define GPCT_SET_GATE 0x0004 00084 #define GPCT_SET_DIRECTION 0x0008 00085 #define GPCT_SET_OPERATION 0x0010 00086 #define GPCT_ARM 0x0020 00087 #define GPCT_DISARM 0x0040 00088 #define GPCT_GET_INT_CLK_FRQ 0x0080 00089 00090 #define GPCT_INT_CLOCK 0x0001 00091 #define GPCT_EXT_PIN 0x0002 00092 #define GPCT_NO_GATE 0x0004 00093 #define GPCT_UP 0x0008 00094 #define GPCT_DOWN 0x0010 00095 #define GPCT_HWUD 0x0020 00096 #define GPCT_SIMPLE_EVENT 0x0040 00097 #define GPCT_SINGLE_PERIOD 0x0080 00098 #define GPCT_SINGLE_PW 0x0100 00099 #define GPCT_CONT_PULSE_OUT 0x0200 00100 #define GPCT_SINGLE_PULSE_OUT 0x0400 00101 00102 /* instructions */ 00103 00104 #define INSN_MASK_WRITE 0x8000000 00105 #define INSN_MASK_READ 0x4000000 00106 #define INSN_MASK_SPECIAL 0x2000000 00107 00108 #define INSN_READ ( 0 | INSN_MASK_READ) 00109 #define INSN_WRITE ( 1 | INSN_MASK_WRITE) 00110 #define INSN_BITS ( 2 | INSN_MASK_READ|INSN_MASK_WRITE) 00111 #define INSN_CONFIG ( 3 | INSN_MASK_READ|INSN_MASK_WRITE) 00112 #define INSN_GTOD ( 4 | INSN_MASK_READ|INSN_MASK_SPECIAL) 00113 #define INSN_WAIT ( 5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL) 00114 #define INSN_INTTRIG ( 6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL) 00115 00116 /* trigger flags */ 00117 /* These flags are used in comedi_trig structures */ 00118 00119 #define TRIG_BOGUS 0x0001 /* do the motions */ 00120 #define TRIG_DITHER 0x0002 /* enable dithering */ 00121 #define TRIG_DEGLITCH 0x0004 /* enable deglitching */ 00122 //#define TRIG_RT 0x0008 /* perform op in real time */ 00123 #define TRIG_CONFIG 0x0010 /* perform configuration, not triggering */ 00124 #define TRIG_WAKE_EOS 0x0020 /* wake up on end-of-scan events */ 00125 //#define TRIG_WRITE 0x0040 /* write to bidirectional devices */ 00126 00127 /* command flags */ 00128 /* These flags are used in comedi_cmd structures */ 00129 00130 #define CMDF_PRIORITY 0x00000008 /* try to use a real-time interrupt while performing command */ 00131 00132 #define TRIG_RT CMDF_PRIORITY /* compatibility definition */ 00133 00134 #define CMDF_WRITE 0x00000040 00135 #define TRIG_WRITE CMDF_WRITE /* compatibility definition */ 00136 00137 #define CMDF_RAWDATA 0x00000080 00138 00139 #define COMEDI_EV_START 0x00040000 00140 #define COMEDI_EV_SCAN_BEGIN 0x00080000 00141 #define COMEDI_EV_CONVERT 0x00100000 00142 #define COMEDI_EV_SCAN_END 0x00200000 00143 #define COMEDI_EV_STOP 0x00400000 00144 00145 #define TRIG_ROUND_MASK 0x00030000 00146 #define TRIG_ROUND_NEAREST 0x00000000 00147 #define TRIG_ROUND_DOWN 0x00010000 00148 #define TRIG_ROUND_UP 0x00020000 00149 #define TRIG_ROUND_UP_NEXT 0x00030000 00150 00151 /* trigger sources */ 00152 00153 #define TRIG_ANY 0xffffffff 00154 #define TRIG_INVALID 0x00000000 00155 00156 #define TRIG_NONE 0x00000001 /* never trigger */ 00157 #define TRIG_NOW 0x00000002 /* trigger now + N ns */ 00158 #define TRIG_FOLLOW 0x00000004 /* trigger on next lower level trig */ 00159 #define TRIG_TIME 0x00000008 /* trigger at time N ns */ 00160 #define TRIG_TIMER 0x00000010 /* trigger at rate N ns */ 00161 #define TRIG_COUNT 0x00000020 /* trigger when count reaches N */ 00162 #define TRIG_EXT 0x00000040 /* trigger on external signal N */ 00163 #define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */ 00164 #define TRIG_OTHER 0x00000100 /* driver defined */ 00165 00166 /* subdevice flags */ 00167 00168 #define SDF_BUSY 0x0001 /* device is busy */ 00169 #define SDF_BUSY_OWNER 0x0002 /* device is busy with your job */ 00170 #define SDF_LOCKED 0x0004 /* subdevice is locked */ 00171 #define SDF_LOCK_OWNER 0x0008 /* you own lock */ 00172 #define SDF_MAXDATA 0x0010 /* maxdata depends on channel */ 00173 #define SDF_FLAGS 0x0020 /* flags depend on channel */ 00174 #define SDF_RANGETYPE 0x0040 /* range type depends on channel */ 00175 #define SDF_MODE0 0x0080 /* can do mode 0 */ 00176 #define SDF_MODE1 0x0100 /* can do mode 1 */ 00177 #define SDF_MODE2 0x0200 /* can do mode 2 */ 00178 #define SDF_MODE3 0x0400 /* can do mode 3 */ 00179 #define SDF_MODE4 0x0800 /* can do mode 4 */ 00180 #define SDF_CMD 0x1000 /* can do commands (deprecated) */ 00181 #define SDF_SOFT_CALIBRATED 0x2000 /* subdevice uses software calibration */ 00182 #define SDF_CMD_WRITE 0x4000 /* can do output commands */ 00183 #define SDF_CMD_READ 0x8000 /* can do input commands */ 00184 00185 #define SDF_READABLE 0x00010000 /* subdevice can be read (e.g. analog input) */ 00186 #define SDF_WRITABLE 0x00020000 /* subdevice can be written (e.g. analog output) */ 00187 #define SDF_WRITEABLE SDF_WRITABLE /* spelling error in API */ 00188 #define SDF_INTERNAL 0x00040000 /* subdevice does not have externally visible lines */ 00189 #define SDF_RT 0x00080000 /* DEPRECATED: subdevice is RT capable */ 00190 #define SDF_GROUND 0x00100000 /* can do aref=ground */ 00191 #define SDF_COMMON 0x00200000 /* can do aref=common */ 00192 #define SDF_DIFF 0x00400000 /* can do aref=diff */ 00193 #define SDF_OTHER 0x00800000 /* can do aref=other */ 00194 #define SDF_DITHER 0x01000000 /* can do dithering */ 00195 #define SDF_DEGLITCH 0x02000000 /* can do deglitching */ 00196 #define SDF_MMAP 0x04000000 /* can do mmap() */ 00197 #define SDF_RUNNING 0x08000000 /* subdevice is acquiring data */ 00198 #define SDF_LSAMPL 0x10000000 /* subdevice uses 32-bit samples */ 00199 #define SDF_PACKED 0x20000000 /* subdevice can do packed DIO */ 00200 /* re recyle these flags for PWM */ 00201 #define SDF_PWM_COUNTER SDF_MODE0 /* PWM can automatically switch off */ 00202 #define SDF_PWM_HBRIDGE SDF_MODE1 /* PWM is signed (H-bridge) */ 00203 00204 00205 00206 /* subdevice types */ 00207 00208 enum comedi_subdevice_type { 00209 COMEDI_SUBD_UNUSED, /* unused by driver */ 00210 COMEDI_SUBD_AI, /* analog input */ 00211 COMEDI_SUBD_AO, /* analog output */ 00212 COMEDI_SUBD_DI, /* digital input */ 00213 COMEDI_SUBD_DO, /* digital output */ 00214 COMEDI_SUBD_DIO, /* digital input/output */ 00215 COMEDI_SUBD_COUNTER, /* counter */ 00216 COMEDI_SUBD_TIMER, /* timer */ 00217 COMEDI_SUBD_MEMORY, /* memory, EEPROM, DPRAM */ 00218 COMEDI_SUBD_CALIB, /* calibration DACs */ 00219 COMEDI_SUBD_PROC, /* processor, DSP */ 00220 COMEDI_SUBD_SERIAL, /* serial IO */ 00221 COMEDI_SUBD_PWM /* PWM */ 00222 }; 00223 00224 /* configuration instructions */ 00225 00226 enum configuration_ids { 00227 INSN_CONFIG_DIO_INPUT = 0, 00228 INSN_CONFIG_DIO_OUTPUT = 1, 00229 INSN_CONFIG_DIO_OPENDRAIN = 2, 00230 INSN_CONFIG_ANALOG_TRIG = 16, 00231 // INSN_CONFIG_WAVEFORM = 17, 00232 // INSN_CONFIG_TRIG = 18, 00233 // INSN_CONFIG_COUNTER = 19, 00234 INSN_CONFIG_ALT_SOURCE = 20, 00235 INSN_CONFIG_DIGITAL_TRIG = 21, 00236 INSN_CONFIG_BLOCK_SIZE = 22, 00237 INSN_CONFIG_TIMER_1 = 23, 00238 INSN_CONFIG_FILTER = 24, 00239 INSN_CONFIG_CHANGE_NOTIFY = 25, 00240 00241 /*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26, 00242 INSN_CONFIG_BIDIRECTIONAL_DATA = 27, 00243 INSN_CONFIG_DIO_QUERY = 28, 00244 INSN_CONFIG_PWM_OUTPUT = 29, 00245 INSN_CONFIG_GET_PWM_OUTPUT = 30, 00246 INSN_CONFIG_ARM = 31, 00247 INSN_CONFIG_DISARM = 32, 00248 INSN_CONFIG_GET_COUNTER_STATUS = 33, 00249 INSN_CONFIG_RESET = 34, 00250 INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, // Use CTR as single pulsegenerator 00251 INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002, // Use CTR as pulsetraingenerator 00252 INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003, // Use the counter as encoder 00253 INSN_CONFIG_SET_GATE_SRC = 2001, // Set gate source 00254 INSN_CONFIG_GET_GATE_SRC = 2002, // Get gate source 00255 INSN_CONFIG_SET_CLOCK_SRC = 2003, // Set master clock source 00256 INSN_CONFIG_GET_CLOCK_SRC = 2004, // Get master clock source 00257 INSN_CONFIG_SET_OTHER_SRC = 2005, // Set other source 00258 // INSN_CONFIG_GET_OTHER_SRC = 2006, // Get other source 00259 INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006, // Get size in bytes of subdevice's on-board fifos used during streaming input/output 00260 INSN_CONFIG_SET_COUNTER_MODE = 4097, 00261 INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE, /* deprecated */ 00262 INSN_CONFIG_8254_READ_STATUS = 4098, 00263 INSN_CONFIG_SET_ROUTING = 4099, 00264 INSN_CONFIG_GET_ROUTING = 4109, 00265 /* PWM */ 00266 INSN_CONFIG_PWM_SET_PERIOD = 5000, /* sets frequency */ 00267 INSN_CONFIG_PWM_GET_PERIOD = 5001, /* gets frequency */ 00268 INSN_CONFIG_GET_PWM_STATUS = 5002, /* is it running? */ 00269 INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, /* sets H bridge: duty cycle and sign bit for a relay at the same time*/ 00270 INSN_CONFIG_PWM_GET_H_BRIDGE = 5004 /* gets H bridge data: duty cycle and the sign bit */ 00271 }; 00272 00273 enum comedi_io_direction { 00274 COMEDI_INPUT = 0, 00275 COMEDI_OUTPUT = 1, 00276 COMEDI_OPENDRAIN = 2 00277 }; 00278 00279 enum comedi_support_level 00280 { 00281 COMEDI_UNKNOWN_SUPPORT = 0, 00282 COMEDI_SUPPORTED, 00283 COMEDI_UNSUPPORTED 00284 }; 00285 00286 /* ioctls */ 00287 00288 #define CIO 'd' 00289 #define COMEDI_DEVCONFIG _IOW(CIO,0,comedi_devconfig) 00290 #define COMEDI_DEVINFO _IOR(CIO,1,comedi_devinfo) 00291 #define COMEDI_SUBDINFO _IOR(CIO,2,comedi_subdinfo) 00292 #define COMEDI_CHANINFO _IOR(CIO,3,comedi_chaninfo) 00293 #define COMEDI_TRIG _IOWR(CIO,4,comedi_trig) 00294 #define COMEDI_LOCK _IO(CIO,5) 00295 #define COMEDI_UNLOCK _IO(CIO,6) 00296 #define COMEDI_CANCEL _IO(CIO,7) 00297 #define COMEDI_RANGEINFO _IOR(CIO,8,comedi_rangeinfo) 00298 #define COMEDI_CMD _IOR(CIO,9,comedi_cmd) 00299 #define COMEDI_CMDTEST _IOR(CIO,10,comedi_cmd) 00300 #define COMEDI_INSNLIST _IOR(CIO,11,comedi_insnlist) 00301 #define COMEDI_INSN _IOR(CIO,12,comedi_insn) 00302 #define COMEDI_BUFCONFIG _IOR(CIO,13,comedi_bufconfig) 00303 #define COMEDI_BUFINFO _IOWR(CIO,14,comedi_bufinfo) 00304 #define COMEDI_POLL _IO(CIO,15) 00305 00306 /* structures */ 00307 00308 typedef struct comedi_trig_struct comedi_trig; 00309 typedef struct comedi_cmd_struct comedi_cmd; 00310 typedef struct comedi_insn_struct comedi_insn; 00311 typedef struct comedi_insnlist_struct comedi_insnlist; 00312 typedef struct comedi_chaninfo_struct comedi_chaninfo; 00313 typedef struct comedi_subdinfo_struct comedi_subdinfo; 00314 typedef struct comedi_devinfo_struct comedi_devinfo; 00315 typedef struct comedi_devconfig_struct comedi_devconfig; 00316 typedef struct comedi_rangeinfo_struct comedi_rangeinfo; 00317 typedef struct comedi_krange_struct comedi_krange; 00318 typedef struct comedi_bufconfig_struct comedi_bufconfig; 00319 typedef struct comedi_bufinfo_struct comedi_bufinfo; 00320 00321 struct comedi_trig_struct { 00322 unsigned int subdev; /* subdevice */ 00323 unsigned int mode; /* mode */ 00324 unsigned int flags; 00325 unsigned int n_chan; /* number of channels */ 00326 unsigned int *chanlist; /* channel/range list */ 00327 sampl_t *data; /* data list, size depends on subd flags */ 00328 unsigned int n; /* number of scans */ 00329 unsigned int trigsrc; 00330 unsigned int trigvar; 00331 unsigned int trigvar1; 00332 unsigned int data_len; 00333 unsigned int unused[3]; 00334 }; 00335 00336 struct comedi_insn_struct { 00337 unsigned int insn; 00338 unsigned int n; 00339 lsampl_t *data; 00340 unsigned int subdev; 00341 unsigned int chanspec; 00342 unsigned int unused[3]; 00343 }; 00344 00345 struct comedi_insnlist_struct { 00346 unsigned int n_insns; 00347 comedi_insn *insns; 00348 }; 00349 00350 struct comedi_cmd_struct { 00351 unsigned int subdev; 00352 unsigned int flags; 00353 00354 unsigned int start_src; 00355 unsigned int start_arg; 00356 00357 unsigned int scan_begin_src; 00358 unsigned int scan_begin_arg; 00359 00360 unsigned int convert_src; 00361 unsigned int convert_arg; 00362 00363 unsigned int scan_end_src; 00364 unsigned int scan_end_arg; 00365 00366 unsigned int stop_src; 00367 unsigned int stop_arg; 00368 00369 unsigned int *chanlist; /* channel/range list */ 00370 unsigned int chanlist_len; 00371 00372 sampl_t *data; /* data list, size depends on subd flags */ 00373 unsigned int data_len; 00374 }; 00375 00376 struct comedi_chaninfo_struct { 00377 unsigned int subdev; 00378 lsampl_t *maxdata_list; 00379 unsigned int *flaglist; 00380 unsigned int *rangelist; 00381 unsigned int unused[4]; 00382 }; 00383 00384 struct comedi_rangeinfo_struct { 00385 unsigned int range_type; 00386 void *range_ptr; 00387 }; 00388 00389 struct comedi_krange_struct { 00390 int min; /* fixed point, multiply by 1e-6 */ 00391 int max; /* fixed point, multiply by 1e-6 */ 00392 unsigned int flags; 00393 }; 00394 00395 00396 struct comedi_subdinfo_struct { 00397 unsigned int type; 00398 unsigned int n_chan; 00399 unsigned int subd_flags; 00400 unsigned int timer_type; 00401 unsigned int len_chanlist; 00402 lsampl_t maxdata; 00403 unsigned int flags; /* channel flags */ 00404 unsigned int range_type; /* lookup in kernel */ 00405 unsigned int settling_time_0; 00406 unsigned insn_bits_support; /* see support_level enum for values*/ 00407 unsigned int unused[8]; 00408 }; 00409 00410 struct comedi_devinfo_struct { 00411 unsigned int version_code; 00412 unsigned int n_subdevs; 00413 char driver_name[COMEDI_NAMELEN]; 00414 char board_name[COMEDI_NAMELEN]; 00415 int read_subdevice; 00416 int write_subdevice; 00417 int unused[30]; 00418 }; 00419 00420 struct comedi_devconfig_struct { 00421 char board_name[COMEDI_NAMELEN]; 00422 int options[COMEDI_NDEVCONFOPTS]; 00423 }; 00424 00425 struct comedi_bufconfig_struct { 00426 unsigned int subdevice; 00427 unsigned int flags; 00428 00429 unsigned int maximum_size; 00430 unsigned int size; 00431 00432 unsigned int unused[4]; 00433 }; 00434 00435 struct comedi_bufinfo_struct { 00436 unsigned int subdevice; 00437 unsigned int bytes_read; 00438 00439 unsigned int buf_write_ptr; 00440 unsigned int buf_read_ptr; 00441 unsigned int buf_write_count; 00442 unsigned int buf_read_count; 00443 00444 unsigned int bytes_written; 00445 00446 unsigned int unused[4]; 00447 }; 00448 00449 /* range stuff */ 00450 00451 #define __RANGE(a,b) ((((a)&0xffff)<<16)|((b)&0xffff)) 00452 00453 #define RANGE_OFFSET(a) (((a)>>16)&0xffff) 00454 #define RANGE_LENGTH(b) ((b)&0xffff) 00455 00456 #define RF_UNIT(flags) ((flags)&0xff) 00457 #define RF_EXTERNAL (1<<8) 00458 00459 #define UNIT_volt 0 00460 #define UNIT_mA 1 00461 #define UNIT_none 2 00462 00463 #define COMEDI_MIN_SPEED ((unsigned int)0xffffffff) 00464 00465 /* callback stuff */ 00466 /* only relevant to kernel modules. */ 00467 00468 #define COMEDI_CB_EOS 1 /* end of scan */ 00469 #define COMEDI_CB_EOA 2 /* end of acquisition */ 00470 #define COMEDI_CB_BLOCK 4 /* DEPRECATED: convenient block size */ 00471 #define COMEDI_CB_EOBUF 8 /* DEPRECATED: end of buffer */ 00472 #define COMEDI_CB_ERROR 16 /* card error during acquisition */ 00473 #define COMEDI_CB_OVERFLOW 32 /* buffer overflow/underflow */ 00474 00475 /**********************************************************/ 00476 /* everything after this line is ALPHA */ 00477 /**********************************************************/ 00478 00479 /* 00480 8254 specific configuration. 00481 00482 It supports two config commands: 00483 00484 0 ID: INSN_CONFIG_SET_COUNTER_MODE 00485 1 8254 Mode 00486 I8254_MODE0, I8254_MODE1, ..., I8254_MODE5 00487 OR'ed with: 00488 I8254_BCD, I8254_BINARY 00489 00490 0 ID: INSN_CONFIG_8254_READ_STATUS 00491 1 <-- Status byte returned here. 00492 B7=Output 00493 B6=NULL Count 00494 B5-B0 Current mode. 00495 00496 */ 00497 00498 enum i8254_mode { 00499 I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */ 00500 I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */ 00501 I8254_MODE2 = (2 << 1), /* Rate generator */ 00502 I8254_MODE3 = (3 << 1), /* Square wave mode */ 00503 I8254_MODE4 = (4 << 1), /* Software triggered strobe */ 00504 I8254_MODE5 = (5 << 1), /* Hardware triggered strobe (retriggerable) */ 00505 I8254_BCD = 1, /* use binary-coded decimal instead of binary (pretty useless) */ 00506 I8254_BINARY = 0 00507 }; 00508 00509 static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel) { 00510 if (pfi_channel < 10) 00511 return 0x1 + pfi_channel; 00512 else 00513 return 0xb + pfi_channel; 00514 } static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel) { 00515 if (rtsi_channel < 7) 00516 return 0xb + rtsi_channel; 00517 else 00518 return 0x1b; 00519 } 00520 /* mode bits for NI general-purpose counters, set with INSN_CONFIG_SET_COUNTER_MODE */ 00521 #define NI_GPCT_COUNTING_MODE_SHIFT 16 00522 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20 00523 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24 00524 enum ni_gpct_mode_bits { 00525 NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4, 00526 NI_GPCT_EDGE_GATE_MODE_MASK = 0x18, 00527 NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0, 00528 NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8, 00529 NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10, 00530 NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18, 00531 NI_GPCT_STOP_MODE_MASK = 0x60, 00532 NI_GPCT_STOP_ON_GATE_BITS = 0x00, 00533 NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20, 00534 NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40, 00535 NI_GPCT_LOAD_B_SELECT_BIT = 0x80, 00536 NI_GPCT_OUTPUT_MODE_MASK = 0x300, 00537 NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100, 00538 NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200, 00539 NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300, 00540 NI_GPCT_HARDWARE_DISARM_MASK = 0xc00, 00541 NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000, 00542 NI_GPCT_DISARM_AT_TC_BITS = 0x400, 00543 NI_GPCT_DISARM_AT_GATE_BITS = 0x800, 00544 NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00, 00545 NI_GPCT_LOADING_ON_TC_BIT = 0x1000, 00546 NI_GPCT_LOADING_ON_GATE_BIT = 0x4000, 00547 NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT, 00548 NI_GPCT_COUNTING_MODE_NORMAL_BITS = 00549 0x0 << NI_GPCT_COUNTING_MODE_SHIFT, 00550 NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS = 00551 0x1 << NI_GPCT_COUNTING_MODE_SHIFT, 00552 NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS = 00553 0x2 << NI_GPCT_COUNTING_MODE_SHIFT, 00554 NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS = 00555 0x3 << NI_GPCT_COUNTING_MODE_SHIFT, 00556 NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS = 00557 0x4 << NI_GPCT_COUNTING_MODE_SHIFT, 00558 NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS = 00559 0x6 << NI_GPCT_COUNTING_MODE_SHIFT, 00560 NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 00561 NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS = 00562 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT, 00563 NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS = 00564 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT, 00565 NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS = 00566 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT, 00567 NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS = 00568 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 00569 NI_GPCT_INDEX_ENABLE_BIT = 0x400000, 00570 NI_GPCT_COUNTING_DIRECTION_MASK = 00571 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 00572 NI_GPCT_COUNTING_DIRECTION_DOWN_BITS = 00573 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 00574 NI_GPCT_COUNTING_DIRECTION_UP_BITS = 00575 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 00576 NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS = 00577 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 00578 NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS = 00579 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 00580 NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000, 00581 NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0, 00582 NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000, 00583 NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000, 00584 NI_GPCT_OR_GATE_BIT = 0x10000000, 00585 NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000 00586 }; 00587 00588 /* Bits for setting a clock source with 00589 * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */ 00590 enum ni_gpct_clock_source_bits { 00591 NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f, 00592 NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0, 00593 NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1, 00594 NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2, 00595 NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3, 00596 NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4, 00597 NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5, 00598 NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6, /* NI 660x-specific */ 00599 NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7, 00600 NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8, 00601 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9, 00602 NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000, 00603 NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0, 00604 NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, /* divide source by 2 */ 00605 NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, /* divide source by 8 */ 00606 NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000 00607 }; 00608 static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n) { /* NI 660x-specific */ 00609 return 0x10 + n; 00610 } 00611 static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n) { 00612 return 0x18 + n; 00613 } 00614 static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n) { /* no pfi on NI 660x */ 00615 return 0x20 + n; 00616 } 00617 00618 /* Possibilities for setting a gate source with 00619 INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters. 00620 May be bitwise-or'd with CR_EDGE or CR_INVERT. */ 00621 enum ni_gpct_gate_select { 00622 /* m-series gates */ 00623 NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0, 00624 NI_GPCT_AI_START2_GATE_SELECT = 0x12, 00625 NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13, 00626 NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14, 00627 NI_GPCT_AI_START1_GATE_SELECT = 0x1c, 00628 NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d, 00629 NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e, 00630 NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f, 00631 /* more gates for 660x */ 00632 NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100, 00633 NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101, 00634 /* more gates for 660x "second gate" */ 00635 NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201, 00636 NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e, 00637 /* m-series "second gate" sources are unknown, 00638 we should add them here with an offset of 0x300 when known. */ 00639 NI_GPCT_DISABLED_GATE_SELECT = 0x8000, 00640 }; 00641 static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n) { 00642 return 0x102 + n; 00643 } 00644 static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n) { 00645 return NI_USUAL_RTSI_SELECT(n); 00646 } 00647 static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n) { 00648 return NI_USUAL_PFI_SELECT(n); 00649 } 00650 static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n) { 00651 return 0x202 + n; 00652 } 00653 00654 /* Possibilities for setting a source with 00655 INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */ 00656 enum ni_gpct_other_index { 00657 NI_GPCT_SOURCE_ENCODER_A, 00658 NI_GPCT_SOURCE_ENCODER_B, 00659 NI_GPCT_SOURCE_ENCODER_Z 00660 }; 00661 enum ni_gpct_other_select { 00662 /* m-series gates */ 00663 // Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT 00664 NI_GPCT_DISABLED_OTHER_SELECT = 0x8000, 00665 }; 00666 static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n) { 00667 return NI_USUAL_PFI_SELECT(n); 00668 } 00669 00670 /* start sources for ni general-purpose counters for use with 00671 INSN_CONFIG_ARM */ 00672 enum ni_gpct_arm_source { 00673 NI_GPCT_ARM_IMMEDIATE = 0x0, 00674 NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter and the adjacent paired counter simultaneously */ 00675 /* NI doesn't document bits for selecting hardware arm triggers. If 00676 the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least significant 00677 bits (3 bits for 660x or 5 bits for m-series) through to the hardware. 00678 This will at least allow someone to figure out what the bits do later. */ 00679 NI_GPCT_ARM_UNKNOWN = 0x1000, 00680 }; 00681 00682 /* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */ 00683 enum ni_gpct_filter_select { 00684 NI_GPCT_FILTER_OFF = 0x0, 00685 NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1, 00686 NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2, 00687 NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3, 00688 NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4, 00689 NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5, 00690 NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6 00691 }; 00692 00693 /* PFI digital filtering options for ni m-series for use with INSN_CONFIG_FILTER. */ 00694 enum ni_pfi_filter_select { 00695 NI_PFI_FILTER_OFF = 0x0, 00696 NI_PFI_FILTER_125ns = 0x1, 00697 NI_PFI_FILTER_6425ns = 0x2, 00698 NI_PFI_FILTER_2550us = 0x3 00699 }; 00700 00701 /* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */ 00702 enum ni_mio_clock_source { 00703 NI_MIO_INTERNAL_CLOCK = 0, 00704 NI_MIO_RTSI_CLOCK = 1, /* doesn't work for m-series, use NI_MIO_PLL_RTSI_CLOCK() */ 00705 /* the NI_MIO_PLL_* sources are m-series only */ 00706 NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2, 00707 NI_MIO_PLL_PXI10_CLOCK = 3, 00708 NI_MIO_PLL_RTSI0_CLOCK = 4 00709 }; 00710 static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel) { 00711 return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel; 00712 } 00713 00714 /* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING. 00715 The numbers assigned are not arbitrary, they correspond to the bits required 00716 to program the board. */ 00717 enum ni_rtsi_routing { 00718 NI_RTSI_OUTPUT_ADR_START1 = 0, 00719 NI_RTSI_OUTPUT_ADR_START2 = 1, 00720 NI_RTSI_OUTPUT_SCLKG = 2, 00721 NI_RTSI_OUTPUT_DACUPDN = 3, 00722 NI_RTSI_OUTPUT_DA_START1 = 4, 00723 NI_RTSI_OUTPUT_G_SRC0 = 5, 00724 NI_RTSI_OUTPUT_G_GATE0 = 6, 00725 NI_RTSI_OUTPUT_RGOUT0 = 7, 00726 NI_RTSI_OUTPUT_RTSI_BRD_0 = 8, 00727 NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI clock on line 7 */ 00728 }; 00729 static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n) { 00730 return NI_RTSI_OUTPUT_RTSI_BRD_0 + n; 00731 } 00732 00733 /* Signals which can be routed to an NI PFI pin on an m-series board 00734 with INSN_CONFIG_SET_ROUTING. These numbers are also returned 00735 by INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though 00736 their routing cannot be changed. The numbers assigned are 00737 not arbitrary, they correspond to the bits required 00738 to program the board. */ 00739 enum ni_pfi_routing { 00740 NI_PFI_OUTPUT_PFI_DEFAULT = 0, 00741 NI_PFI_OUTPUT_AI_START1 = 1, 00742 NI_PFI_OUTPUT_AI_START2 = 2, 00743 NI_PFI_OUTPUT_AI_CONVERT = 3, 00744 NI_PFI_OUTPUT_G_SRC1 = 4, 00745 NI_PFI_OUTPUT_G_GATE1 = 5, 00746 NI_PFI_OUTPUT_AO_UPDATE_N = 6, 00747 NI_PFI_OUTPUT_AO_START1 = 7, 00748 NI_PFI_OUTPUT_AI_START_PULSE = 8, 00749 NI_PFI_OUTPUT_G_SRC0 = 9, 00750 NI_PFI_OUTPUT_G_GATE0 = 10, 00751 NI_PFI_OUTPUT_EXT_STROBE = 11, 00752 NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12, 00753 NI_PFI_OUTPUT_GOUT0 = 13, 00754 NI_PFI_OUTPUT_GOUT1 = 14, 00755 NI_PFI_OUTPUT_FREQ_OUT = 15, 00756 NI_PFI_OUTPUT_PFI_DO = 16, 00757 NI_PFI_OUTPUT_I_ATRIG = 17, 00758 NI_PFI_OUTPUT_RTSI0 = 18, 00759 NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26, 00760 NI_PFI_OUTPUT_SCXI_TRIG1 = 27, 00761 NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28, 00762 NI_PFI_OUTPUT_CDI_SAMPLE = 29, 00763 NI_PFI_OUTPUT_CDO_UPDATE = 30 00764 }; 00765 static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel) { 00766 return NI_PFI_OUTPUT_RTSI0 + rtsi_channel; 00767 } 00768 00769 /* Signals which can be routed to output on a NI PFI pin on a 660x board 00770 with INSN_CONFIG_SET_ROUTING. The numbers assigned are 00771 not arbitrary, they correspond to the bits required 00772 to program the board. Lines 0 to 7 can only be set to 00773 NI_660X_PFI_OUTPUT_DIO. Lines 32 to 39 can only be set to 00774 NI_660X_PFI_OUTPUT_COUNTER. */ 00775 enum ni_660x_pfi_routing { 00776 NI_660X_PFI_OUTPUT_COUNTER = 1, // counter 00777 NI_660X_PFI_OUTPUT_DIO = 2, // static digital output 00778 }; 00779 00780 /* NI External Trigger lines. These values are not arbitrary, but are related to 00781 the bits required to program the board (offset by 1 for historical reasons). */ 00782 static inline unsigned NI_EXT_PFI(unsigned pfi_channel) { 00783 return NI_USUAL_PFI_SELECT(pfi_channel) - 1; 00784 } 00785 static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel) { 00786 return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1; 00787 } 00788 00789 /* status bits for INSN_CONFIG_GET_COUNTER_STATUS */ 00790 enum comedi_counter_status_flags { 00791 COMEDI_COUNTER_ARMED = 0x1, 00792 COMEDI_COUNTER_COUNTING = 0x2, 00793 COMEDI_COUNTER_TERMINAL_COUNT = 0x4, 00794 }; 00795 00796 /* Clock sources for CDIO subdevice on NI m-series boards. 00797 Used as the scan_begin_arg for a comedi_command. These 00798 sources may also be bitwise-or'd with CR_INVERT to change polarity. */ 00799 enum ni_m_series_cdio_scan_begin_src { 00800 NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0, 00801 NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18, 00802 NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19, 00803 NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20, 00804 NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28, 00805 NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29, 00806 NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30, 00807 NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31, 00808 NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32, 00809 NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33 00810 }; 00811 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) { 00812 return NI_USUAL_PFI_SELECT(pfi_channel); 00813 } 00814 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned 00815 rtsi_channel) { 00816 return NI_USUAL_RTSI_SELECT(rtsi_channel); 00817 } 00818 00819 /* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command 00820 on NI boards. These scan begin sources can also be bitwise-or'd with 00821 CR_INVERT to change polarity. */ 00822 static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) { 00823 return NI_USUAL_PFI_SELECT(pfi_channel); 00824 } 00825 static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel) { 00826 return NI_USUAL_RTSI_SELECT(rtsi_channel); 00827 } 00828 00829 /* Bits for setting a clock source with 00830 * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */ 00831 enum ni_freq_out_clock_source_bits { 00832 NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, // 10 MHz 00833 NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC // 100 KHz 00834 }; 00835 00836 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for 00837 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */ 00838 enum amplc_dio_clock_source { 00839 AMPLC_DIO_CLK_CLKN, /* per channel external clock 00840 input/output pin (pin is only an 00841 input when clock source set to this 00842 value, otherwise it is an output) */ 00843 AMPLC_DIO_CLK_10MHZ, /* 10 MHz internal clock */ 00844 AMPLC_DIO_CLK_1MHZ, /* 1 MHz internal clock */ 00845 AMPLC_DIO_CLK_100KHZ, /* 100 kHz internal clock */ 00846 AMPLC_DIO_CLK_10KHZ, /* 10 kHz internal clock */ 00847 AMPLC_DIO_CLK_1KHZ, /* 1 kHz internal clock */ 00848 AMPLC_DIO_CLK_OUTNM1, /* output of preceding counter channel 00849 (for channel 0, preceding counter 00850 channel is channel 2 on preceding 00851 counter subdevice, for first counter 00852 subdevice, preceding counter 00853 subdevice is the last counter 00854 subdevice) */ 00855 AMPLC_DIO_CLK_EXT /* per chip external input pin */ 00856 }; 00857 00858 /* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for 00859 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */ 00860 enum amplc_dio_gate_source { 00861 AMPLC_DIO_GAT_VCC, /* internal high logic level */ 00862 AMPLC_DIO_GAT_GND, /* internal low logic level */ 00863 AMPLC_DIO_GAT_GATN, /* per channel external gate input */ 00864 AMPLC_DIO_GAT_NOUTNM2, /* negated output of counter channel 00865 minus 2 (for channels 0 or 1, 00866 channel minus 2 is channel 1 or 2 on 00867 the preceding counter subdevice, for 00868 the first counter subdevice the 00869 preceding counter subdevice is the 00870 last counter subdevice) */ 00871 AMPLC_DIO_GAT_RESERVED4, 00872 AMPLC_DIO_GAT_RESERVED5, 00873 AMPLC_DIO_GAT_RESERVED6, 00874 AMPLC_DIO_GAT_RESERVED7 00875 }; 00876 00877 #ifdef __cplusplus 00878 } 00879 #endif 00880 00881 #endif /* _COMEDI_H */
1.7.4 
