RTXI 1.3
comedi/comedi/drivers/dt9812.h
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00001 #ifndef __DT9812_H__
00002 #define __DT9812_H__
00003 
00004 #define DT9812_DIAGS_BOARD_INFO_ADDR        0xFBFF
00005 #define DT9812_MAX_WRITE_CMD_PIPE_SIZE      32
00006 #define DT9812_MAX_READ_CMD_PIPE_SIZE       32
00007 
00008 /*
00009  * See Silican Laboratories C8051F020/1/2/3 manual
00010  */
00011 #define F020_SFR_P4                       0x84
00012 #define F020_SFR_P1                       0x90
00013 #define F020_SFR_P2                       0xa0
00014 #define F020_SFR_P3                       0xb0
00015 #define F020_SFR_AMX0CF                   0xba
00016 #define F020_SFR_AMX0SL                   0xbb
00017 #define F020_SFR_ADC0CF                   0xbc
00018 #define F020_SFR_ADC0L                    0xbe
00019 #define F020_SFR_ADC0H                    0xbf
00020 #define F020_SFR_DAC0L                    0xd2
00021 #define F020_SFR_DAC0H                    0xd3
00022 #define F020_SFR_DAC0CN                   0xd4
00023 #define F020_SFR_DAC1L                    0xd5
00024 #define F020_SFR_DAC1H                    0xd6
00025 #define F020_SFR_DAC1CN                   0xd7
00026 #define F020_SFR_ADC0CN                   0xe8
00027 
00028 #define F020_MASK_ADC0CF_AMP0GN0          0x01
00029 #define F020_MASK_ADC0CF_AMP0GN1          0x02
00030 #define F020_MASK_ADC0CF_AMP0GN2          0x04
00031 
00032 #define F020_MASK_ADC0CN_AD0EN            0x80
00033 #define F020_MASK_ADC0CN_AD0INT           0x20
00034 #define F020_MASK_ADC0CN_AD0BUSY          0x10
00035 
00036 #define F020_MASK_DACxCN_DACxEN           0x80
00037 
00038 typedef enum {                  //                      A/D      D/A     DI   DO    CT
00039         DT9812_DEVID_DT9812_10, //    8        2       8    8     1   +/- 10V
00040         DT9812_DEVID_DT9812_2PT5,       //    8        2       8    8     1   0-2.44V
00041 #if 0
00042         DT9812_DEVID_DT9813,    //    16       2       4    4     1   +/- 10V 
00043         DT9812_DEVID_DT9814     //    24       2       0    0     1   +/- 10V
00044 #endif
00045 } dt9812_devid_t;
00046 
00047 typedef enum {
00048         DT9812_GAIN_0PT25 = 1,
00049         DT9812_GAIN_0PT5 = 2,
00050         DT9812_GAIN_1 = 4,
00051         DT9812_GAIN_2 = 8,
00052         DT9812_GAIN_4 = 16,
00053         DT9812_GAIN_8 = 32,
00054         DT9812_GAIN_16 = 64,
00055 } dt9812_gain_t;
00056 
00057 typedef enum {
00058         DT9812_LEAST_USB_FIRMWARE_CMD_CODE = 0,
00059         DT9812_W_FLASH_DATA = 0,        // Write Flash memory
00060         DT9812_R_FLASH_DATA = 1,        // Read Flash memory (misc config info)
00061 
00062         // Register read/write commands for processor
00063         DT9812_R_SINGLE_BYTE_REG = 2,   // Read a single byte of USB memory
00064         DT9812_W_SINGLE_BYTE_REG = 3,   // Write a single byte of USB memory
00065         DT9812_R_MULTI_BYTE_REG = 4,    // Multiple Reads of USB memory
00066         DT9812_W_MULTI_BYTE_REG = 5,    // Multiple Writes of USB memory
00067         DT9812_RMW_SINGLE_BYTE_REG = 6, // Read, (AND) with mask, OR value, 
00068         // then write (single)
00069         DT9812_RMW_MULTI_BYTE_REG = 7,  // Read, (AND) with mask, OR value, 
00070         // then write (multiple)
00071 
00072         // Register read/write commands for SMBus
00073         DT9812_R_SINGLE_BYTE_SMBUS = 8, // Read a single byte of SMBus
00074         DT9812_W_SINGLE_BYTE_SMBUS = 9, // Write a single byte of SMBus
00075         DT9812_R_MULTI_BYTE_SMBUS = 10, // Multiple Reads of SMBus
00076         DT9812_W_MULTI_BYTE_SMBUS = 11, // Multiple Writes of SMBus
00077 
00078         // Register read/write commands for a device 
00079         DT9812_R_SINGLE_BYTE_DEV = 12,  // Read a single byte of a device
00080         DT9812_W_SINGLE_BYTE_DEV = 13,  // Write a single byte of a device
00081         DT9812_R_MULTI_BYTE_DEV = 14,   // Multiple Reads of a device
00082         DT9812_W_MULTI_BYTE_DEV = 15,   // Multiple Writes of a device
00083 
00084         DT9812_W_DAC_THRESHOLD = 16,    // Not sure if we'll need this
00085 
00086         DT9812_W_INT_ON_CHANGE_MASK = 17,       // Set interrupt on change mask
00087 
00088         DT9812_W_CGL = 18,      // Write (or Clear) the CGL for the ADC
00089         DT9812_R_MULTI_BYTE_USBMEM = 19,        // Multiple Reads of USB memory
00090         DT9812_W_MULTI_BYTE_USBMEM = 20,        // Multiple Writes to USB memory
00091 
00092         DT9812_START_SUBSYSTEM = 21,    // Issue a start command to a 
00093         // given subsystem 
00094         DT9812_STOP_SUBSYSTEM = 22,     // Issue a stop command to a 
00095         // given subsystem 
00096 
00097         DT9812_CALIBRATE_POT = 23,      //calibrate the board using CAL_POT_CMD
00098         DT9812_W_DAC_FIFO_SIZE = 24,    // set the DAC FIFO size
00099         DT9812_W_CGL_DAC = 25,  // Write (or Clear) the CGL for the DAC
00100         DT9812_R_SINGLE_VALUE_CMD = 26, // Read a single value from a subsystem
00101         DT9812_W_SINGLE_VALUE_CMD = 27, // Write a single value to a subsystem
00102         DT9812_MAX_USB_FIRMWARE_CMD_CODE        // Valid DT9812_USB_FIRMWARE_CMD_CODE's 
00103                 // will be less than this number
00104 } dt9812_usb_firmware_cmd_t;
00105 
00106 typedef struct {
00107         u16 numbytes;
00108         u16 address;
00109 } dt9812_flash_data_t;
00110 
00111 #define DT9812_MAX_NUM_MULTI_BYTE_RDS  \
00112     ((DT9812_MAX_WRITE_CMD_PIPE_SIZE - 4 - 1) / sizeof(u8))
00113 
00114 typedef struct {
00115         u8 count;
00116         u8 address[DT9812_MAX_NUM_MULTI_BYTE_RDS];
00117 } dt9812_read_multi_t;
00118 
00119 typedef struct {
00120         u8 address;
00121         u8 value;
00122 } dt9812_write_byte_t;
00123 
00124 #define DT9812_MAX_NUM_MULTI_BYTE_WRTS  \
00125     ((DT9812_MAX_WRITE_CMD_PIPE_SIZE - 4 - 1) / sizeof(dt9812_write_byte_t))
00126 
00127 typedef struct {
00128         u8 count;
00129         dt9812_write_byte_t write[DT9812_MAX_NUM_MULTI_BYTE_WRTS];
00130 } dt9812_write_multi_t;
00131 
00132 typedef struct {
00133         u8 address;
00134         u8 and_mask;
00135         u8 or_value;
00136 } dt9812_rmw_byte_t;
00137 
00138 #define DT9812_MAX_NUM_MULTI_BYTE_RMWS  \
00139     ((DT9812_MAX_WRITE_CMD_PIPE_SIZE - 4 - 1) / sizeof(dt9812_rmw_byte_t))
00140 
00141 typedef struct {
00142         u8 count;
00143         dt9812_rmw_byte_t rmw[DT9812_MAX_NUM_MULTI_BYTE_RMWS];
00144 } dt9812_rmw_multi_t;
00145 
00146 typedef struct dt9812_usb_cmd {
00147 
00148         u32 cmd;
00149         union {
00150                 dt9812_flash_data_t flash_data_info;
00151                 dt9812_read_multi_t read_multi_info;
00152                 dt9812_write_multi_t write_multi_info;
00153                 dt9812_rmw_multi_t rmw_multi_info;
00154         } u;
00155 #if 0
00156         WRITE_BYTE_INFO WriteByteInfo;
00157         READ_BYTE_INFO ReadByteInfo;
00158         WRITE_MULTI_INFO WriteMultiInfo;
00159         READ_MULTI_INFO ReadMultiInfo;
00160         RMW_BYTE_INFO RMWByteInfo;
00161         RMW_MULTI_INFO RMWMultiInfo;
00162         DAC_THRESHOLD_INFO DacThresholdInfo;
00163         INT_ON_CHANGE_MASK_INFO IntOnChangeMaskInfo;
00164         CGL_INFO CglInfo;
00165         SUBSYSTEM_INFO SubsystemInfo;
00166         CAL_POT_CMD CalPotCmd;
00167         WRITE_DEV_BYTE_INFO WriteDevByteInfo;
00168         READ_DEV_BYTE_INFO ReadDevByteInfo;
00169         WRITE_DEV_MULTI_INFO WriteDevMultiInfo;
00170         READ_DEV_MULTI_INFO ReadDevMultiInfo;
00171         READ_SINGLE_VALUE_INFO ReadSingleValueInfo;
00172         WRITE_SINGLE_VALUE_INFO WriteSingleValueInfo;
00173 #endif
00174 } dt9812_usb_cmd_t;
00175 
00176 #endif
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